Table of Contents
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Figures
6-1
Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-2
Consecutive Numbering of Slots in a Single-Tier Configuration
6-3
Slot Numbering in a Multi-Tier Configuration
6-4
Configuration of a Digital Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-5
Address Assignment for Analog Modules . . . . . . . . . . . . . . . . . . . . . . . . .
6-6
Accesses to the PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-7
Accesses to the PIQ
6-8
Loading the Signal States of the Onboard Inputs and Outputs
6-9
Accesses to the Interrupt PII
6-10 Accesses to the Interrupt PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
6-1
Address Assignment (Subunit A)
6-2
Address Assignment (Subunit B)
6-3
Structure of the Process Image Input Table (PII) and the Process
Image Output Table (PIQ)
6-4
S5-95F: Structure of the PII and PIQ . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-5
RAM in the S5-95F
6-6
Address Assignment in the System Data Area of the S5-95F
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EWA 4NEB 812 6210-02
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Table of Contents
