Figure 65: Interrupt Execution Considerations - GE PACSystems RX7i Reference Manual

Appendix A. Performance Data
I/O Interrupt Block Performance and Sweep Impact Times
Sweep Impact Item
I/O interrupt sweep impact
Minimum response time
Typical response time
Maximum response time
Note that the min, typical, and max response times include a 300 µs Input card filter time.
Dropped Interrupts
When multiple interrupts are triggered during the interrupt latency period, it is possible that interrupt
blocks will only be executed one time even though the interrupt trigger has occurred more than once.
The likelihood of this occurring will increase if the system interrupt latency has increased due to the
specific configuration and use of the system.
This will not cause the CPU to miss a given interrupt; just consolidate the number of times an interrupt
block is executed even though the interrupt stimulus had occurred more than one time.
Interrupt
Logic
Suspended

Figure 65: Interrupt Execution Considerations

109
Performance data not available for this release.
298
CPE302 CPU310
CPE305 (µs)
CPE310
(µs)
109
-
—
PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual
CPU315/ CPE010
CPU320 (µs)
(µs)
127.8 - 309.7
151.7 326.1 392.4
175.0 327.3 396.1
302.7 346.2 434.9
Interrupt Trigger
Interrupt Logic Block
Higher-priority event
CPE020 CPE030 CPE040
(µs) (µs) (µs)
335 125.6
334 330.6
336 331.5
359 375.1
GFK-2222AD
24.0
315.2
315.5
325.7