Automation & Controls Programmable Control Products RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD April 2018 For Public Disclosure...
Changes, modifications, and/or improvements to equipment and specifications are made periodically and these changes may or may not be reflected herein. It is understood that GE may make changes, modifications, or improvements to the equipment referenced herein or to the document itself at any time.
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Table of Contents RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD Table of Contents ............................i Table of Figures ............................vi Chapter 1 Introduction ........................1 Revisions in this Manual ....................... 2 PACSystems Control System Overview ................5 1.2.1 Programming and Configuration ............................ 5 1.2.2 Process Systems ..................................
Contents RX7i CPU Features and Specifications ................84 2.3.1 CPE030/CRE030 and CPE040/CRE040........................89 2.3.2 CPE010, CPE020 and CRE020 ............................91 2.3.3 RX7i Embedded Ethernet Interface ..........................93 RSTi-EP CPU Features and Specifications ............... 98 2.4.1 CPE100/CPE115 ................................101 Chapter 3 CPU Configuration .....................
Contents 4.5.3 RUN/STOP Switch Operation ............................152 Flash Memory Operation ....................153 Logic/Configuration Source and CPU Operating Mode at Power-Up ......154 4.7.1 CPU Mode when Memory Not Preserved/Power-up Source is Flash ............155 4.7.2 CPU Mode when Memory Preserved ........................156 Clocks and Timers ......................
Contents Chapter 6 Serial I/O, SNP & RTU Protocols ................201 Configuring Serial Ports Using COMMREQ Function 65520 ........202 6.1.1 COMMREQ Function Example ............................ 202 6.1.2 Timing ....................................202 6.1.3 Sending Another COMMREQ to the Same Port ....................202 6.1.4 Invalid Port Configuration Combinations ......................
Contents A-2.3 RX3i & RSTi-EP Instruction Times ..........................263 A-2.4 RX7i Instruction Times ..............................264 A-3 Overhead Sweep Impact Times ....................275 A-3.1 Base Sweep Times ................................276 A-3.2 What the Sweep Impact Tables Contain ....................... 278 A-3.3 Programmer Sweep Impact Times ........................... 279 A-3.4 I/O Scan and I/O Fault Sweep Impact ........................
2. PACSystems RX3i System Manual, GFK-2314. 3. RSTi-EP User Manual, GFK-2958. CPU Programming is covered in PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950. It provides an overview of program structure and describes the various languages which may be used, their syntax and operation, and provides examples.
Chapter 1. Introduction Revisions in this Manual Note: A given feature may not be implemented on all PACSystems CPUs. To determine whether a feature is available on a given CPU model and firmware version, please refer to the Important Product Information (IPI) document provided for the CPU version that you are using. Date Description ▪...
▪ Serial Port Electrical Isolation ▪ Removed original Chapters 5-11 (chapters dealing with CPU programming) and Chapter 14 (Diagnostics). These are now in PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 (Chapters 2-8 and Chapter 9 respectively). ▪ Nov- New Section, A-3.6 for EGD Sweep Impact for RX3i CPE302/CPE305/CPE310 and RSTi-EP...
– Chapter 6 ▪ Diagnostics for PROFINET alarms and PROFINET network faults, including #PNIO_ALARM, SA0030 – refer to PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 3 & Chapter 9. ▪ Instruction executions times measured for RX3i CPU320/CRU320 – Appendix A ▪...
Chapter 1. Introduction PACSystems Control System Overview The PACSystems controller environment combines performance, productivity, openness and flexibility. The PACSystems control system integrates advanced technology with existing systems. The result is seamless migration that protects your investment in I/O and application development. 1.2.1 Programming and Configuration Proficy* Machine Edition programming software provides a universal engineering development environment for all programming, configuration and diagnostics of PACSystems.
The RX3i CPE302/CPE305/CPE310 embedded Ethernet interface provides a maximum of two programmer connections. It does not support the full set of Ethernet interface features described in this manual. For a summary of RX3i embedded Ethernet interface features, refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224K or later.
Chapter 1. Introduction Family Catalog Number Description RX7i CPUs with embedded IC698CPE010 300MHz, Celeron CPU, 10MB Ethernet Interface user memory IC698CPE020 700MHz, Pentium CPU, 10 MB user memory IC698CPE030 600MHz, Pentium-M CPU, 64MB user memory IC698CPE040 1800MHz, Pentium-M CPU, 64MB user memory RX7i Redundancy CPUs with IC698CRE020 700MHz, Pentium CPU, 10 MB...
Effective with CPE310/CPE305 firmware version 8.20, or CPE330 firmware version 8.45, the CPE embedded Ethernet port supports OPC UA Server. This feature is available on all firmware versions of CPE400. Refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK- 2224 version M or higher (Chapter 10).
32 SRTP channels with a maximum of 48 simultaneous SRTP server connections. It also supports Modbus TCP. For details on Ethernet Interface capabilities, refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224.
CPE330 firmware version 9.21, the CPE embedded Ethernet interface supports Simple Network Time Protocol (SNTP) Client, Coordinated Universal Time (UTC), and Daylight Savings Time (DST). Refer to PACSystems RX7i, RX3i and RSTi-EP TCP/IP Ethernet Communications User Manual, GFK-2224 version Q or higher.
The CPU Ethernet Interface provides basic remote control system monitoring from a web browser and allows a combined total of up to 16 web server and FTP connections. For details on Ethernet Interface capabilities, refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224.
The RSTi-EP CPE100/CPE115 also embeds an industry standard PROFINET controller that allows it to connect to any type of PROFINET I/O solutions either from GE or any third party. It offers enhanced productivity, flexibility and performance advantages for virtually any type of control application in a range of industries.
Manual, GFK-2314. ▪ The RX7i supports most existing Series 90-70 modules, expansion racks and Genius networks. For a list of supported I/O, Communications, and Intelligent modules, see the PACSystems RX7i Installation Manual, GFK-2223. ▪ Conversion of Series 90-70 and Series 90-30 programs preserves existing development effort.
PACSystems RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222 PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual GFK-2950 PACSystems RX7i, RX3i and RSTi-EP TCP/IP Ethernet Communications User Manual GFK-2224 PACSystems TCP/IP Ethernet Communications Station Manager User Manual GFK-2225 C Programmer’s Toolkit for PACSystems GFK-2259 PACSystems Memory Xchange Modules User’s Manual...
Genius I/O Analog and Discrete Blocks User’s Manual GEK-90486-2 In addition to these manuals, datasheets and product update documents describe individual modules and product revisions. The most recent PACSystems documentation is available on GE’s Automation and Controls support website www.geautomation.com.
Chapter 2 CPU Features & Specifications This chapter provides details on the hardware features of the PACSystems CPUs and their specifications. ▪ Common CPU Features ▪ RX3i CPU Features and Specifications ▪ RX7i CPU Features and Specifications ▪ RSTi-EP CPU Features and Specifications GFK-2222AD April 2018...
Chapter 2. CPU Features & Specifications Common CPU Features 2.1.1 Features Shared by All PACSystems CPU Models ▪ Programming in Ladder Diagram, Function Block Diagram, Structured Text and C. ▪ Floating point (real) data functions. ▪ Configurable data and program memory. ▪...
Chapter 2. CPU Features & Specifications 2.1.2 Features Shared by Certain PACSystems CPU Models ▪ Rx3i CPE302, CPE305, CPE310, CPE330 and CPE400 offer battery-less retention of user memory when each is connected to its compatible Energy Pack. ▪ RSTi-EP CPE100/CPE115 offers battery-less retention of user memory with the support of internal super capacitors.
Chapter 2. CPU Features & Specifications 2.1.3 Firmware Storage in Flash Memory The CPU uses non-volatile flash memory for storing the operating system firmware. This allows firmware to be updated without disassembling the module or replacing EPROMs. The operating system firmware is updated by connecting to the CPU with a PC compatible computer and running the software included with the firmware upgrade kit.
Chapter 2. CPU Features & Specifications 2.1.6 Embedded PROFINET Controller The following CPUs support a feature that permits an Ethernet LAN to be configured for use as a PROFINET Controller: • RX3i CPE400 • Rx3i CPE330 • RSTi-EP CPE100/CPE115 If the Embedded PROFINET Controller feature is to be configured, it must be configured on LAN2 for the CPUs listed above.
Open Productivity and Connectivity Unified Architecture (OPC UA) Server communications on the embedded Ethernet port only. For more information on OPC UA support refer to PACSystems RX7i, RX3i and RSTi-EP TCP/IP Ethernet Communications User Manual, GFK-2224 version M or higher (Chapter 10).
Chapter 2. CPU Features & Specifications 2.1.8 Removable Data Storage Devices (RDSDs) The RX3i CPE302/CPE305/CPE310/CPE330 and CPE400 CPUsprovide the ability to transfer applications to and from Removable Data Storage Devices (RDSD). Typically, these are USB-compatible devices, such as a memory stick, smart phone, digital camera or an MP3 device. Once the data is copied to the RDSD, it can be written to other RX3i / RSTi-EP CPUs of the same type.
Chapter 2. CPU Features & Specifications Uploading a Project from the CPU to the RDSD Notes: Only one application project can be stored to the RDSD at a time. Before the RX3i writes the project to the RDSD, any previous application is removed; if a directory named PACS_Folder exists on the RDSD at the start of the upload, it is deleted with all of its contents.
Chapter 2. CPU Features & Specifications Downloading a Project from the RDSD to the CPU To download a project to the RX3i, the RDSD must contain a valid project, consisting of the hardware configuration, application logic, and reference memory in a compiled format (originating from another RX3i controller).
Chapter 2. CPU Features & Specifications Using an Options.txt File to Modify Download Operation An options.txt file can be used to modify the operation of the RDSD during a store to the RX3i. This is a plain-text file which can contain some or all of the following statements, in any order. The format of each option line is the option keyword, followed by a space, followed by either a capital Y or a capital N.
Chapter 2. CPU Features & Specifications Security When the application is written to the RDSD from a controller that has passwords and/or an OEM key defined, the passwords and OEM key are encrypted and stored on the RDSD. When the project is written from the RDSD to a CPE302/CPE305/CPE310/CPE330 , the passwords and OEM key are copied to it.
Chapter 2. CPU Features & Specifications 2.1.9 CPU Over-Temperature Monitoring and Behavior RX3i CPE302, CPE305, CPE310, CPE330, and CPE400 models monitor the internal temperature of the CPU. • If the temperature rises to a near-critical level, these CPUs set the CPU Over Temperature Fault (refer to section 3.2.7).
Chapter 2. CPU Features & Specifications RX3i CPU Features and Specifications CPU320/ CPE302 CPU310 CPU315 CPE310 CPE330 CPE400 CRU320 CPE305 Discontinued - Discontinued - Discontinued - Lifecycle Phase use CPE310 Active Active Active Active use CPE310 use CPE330 or CPE330 1.1 GHz Intel 1.1 GHz Intel 1 GHz AMD...
Chapter 2. CPU Features & Specifications CPU320/ CPE302 CPU310 CPU315 CPE310 CPE330 CPE400 CRU320 CPE305 Firmware Upgrade v7.30 & later: v7.30 & later: <---------------WinLoader/Serial Port---------------> Web Interface Web Interface CPU Firmware Upgrade Mechanism earlier: earlier: Ethernet Port Ethernet Port WinLoader/ WinLoader/ Serial Port Serial Port...
Note: Whenever the size of any reference memory is changed, the content of the corresponding reference memory is automatically cleared. For discussion of memory types and how they are managed, refer to PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 3.
RTC Battery Life expectancy 5 years Refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224M or later for supported AUPs. The Advanced User Parameters (AUP) feature has been incorporated into PME Hardware Configuration (HWC) effective with PME release 8.60 SIM5.
PROFINET IO-Controller Manual, GFK-2571F or later. For a discussion of OPC UA, refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224M Chapter 10. Supports up to 5 concurrent sessions with up to 10 concurrent variable subscriptions and up to 12,500 Variables.
Chapter 2. CPU Features & Specifications CPU320/ CPE302 CPU310 CPU315 CPE310 CPE330 CPE400 CRU320 CPE305 Model Configurable Configurable Redundancy Features CRU320 only in CPE330 in CPE400 Single bit Single bit Single bit Memory Error Checking and Correction correcting & correcting & correcting &...
The physical features of the CPE400 are shown in Figure 2 and Figure 3. Figure 2: CPE400 Front View and Features The PACSystems* RX3i CPE400, part of GE’s Industrial Internet Control System, is the industry’s first outcome optimizing controller. It augments real-time deterministic control with Field Agent technology, delivering near real time advice through market analysis, fleet and enterprise data, or asset/process knowledge to optimize the outcomes that today’s businesses require.
Chapter 2. CPU Features & Specifications • The stand-alone CPE400 uses a 1.2GHz quad-core microprocessor and real-time hypervisor technology to run real time deterministic control applications concurrently with Field Agent technology without any adverse impact of one over the other. •...
Stop Disabled, Run Enabled, Stop Enabled, Run Disabled, Stop Faulted, and Stop Halted. The Sweep Time variable reports the sweep time in seconds. These variables are located under GE Device Information -> PACSystems RX3i -> Controller. • An OLED display that provides access to basic CPE400 status and control information including each LAN’s configured IP Address.
Chapter 2. CPU Features & Specifications Switches CPE400 All user-accessible switches are provided as pushbuttons on the front panel, as described in the following table. Pushbutton Function DISP Permits user to navigate menus in the OLED display. Permits user to select the menu item on the OLED display. Activates OLED Menu to select RUN/Enabled or RUN/Disabled Mode for the embedded PLC.
Chapter 2. CPU Features & Specifications Figure 3: CPE400 Underside Ports & Connectors GFK-2222AD April 2018...
Chapter 2. CPU Features & Specifications Status Indicator LEDs LED State Operating State On Green PLC is in RUN mode. PLC is in STOP mode. Blinking in unison CPU is updating an internal programmable hardware device. PHY PRES On Green TPM Physical Presence (not functional).
Chapter 2. CPU Features & Specifications Micro-SD Card Interface The Micro SD Card slot is located on the right-hand side of the equipment (Figure 2), level with the OLED display. This port is not functional at time of publication. Once functional, it will support the Removable Data Storage Device features discussed in Section 2.1.8.
Chapter 2. CPU Features & Specifications USB 3.0 Interface The USB ports are not functional at time of publication. Once functional, they will support the Removable Data Storage Device features discussed in Section 2.1.8. Two USB ports, using standard USB Type A connectors (Figure 2), are located on the faceplate below the OLED display.
LAN1 and LAN2 may be used to communicate with the PME programming software using the Service Request Transport Protocol (SRTP, a proprietary GE protocol, used primarily for communication with the programmer). The EFA port cannot be used for this purpose.
Chapter 2. CPU Features & Specifications Two LEDs are integrated into each RJ45 connector. These LEDs indicate the link status and link speed, as follows: Ethernet Indicators (LAN1, LAN2, LAN3 RJ45 Built-in LEDs) LED State Operating State Link On Green The corresponding link has been established.
Chapter 2. CPU Features & Specifications Field Agent The Embedded Field Agent (EFA) port on the underside of CPE400 (Figure 3) is an Ethernet port dedicated to the Field Agent functionality. Figure 5: Typical Field Agent Application Figure 5 shows a typical Field Agent application, in which the role of the CPE400 Embedded Field Agent (EFA) is to gather data locally, then securely transfer selected data to the Predix Cloud via the EFA port.
Chapter 2. CPU Features & Specifications Field Agent Configuration Start the Embedded Field Agent (EFA) After providing the CPE400 with power, the Embedded Field Agent (EFA) application will begin to boot. The FAOK LED will start blinking to indicate when the EFA has booted and is ready for user logins. (This may take about two minutes.) Log into the Web Console To log into the Web Console:...
Chapter 2. CPU Features & Specifications A prompt to change the default password displays. Complete the form to change the default password. Figure 7: Predix Change Password The password complexity requirements display if the chosen password is not sufficiently complex. After changing the password, log in using the new password.
Chapter 2. CPU Features & Specifications Configure the Network EFA IP Addresses By default, the Embedded Field Agent’s WAN interface is set to a static address of 172.31.0.100 with a subnet mask of 255.255.0.0. To change the WAN IP address Verify that the WAN Ethernet cable is connected to the IICS Cloud port / EFA Port.
Chapter 2. CPU Features & Specifications Configure a Network Proxy A Network Proxy is only required when your network architecture is configured to restrict access directly to the Internet. Contact your network administrator for the Network Proxy information. If a network HTTP/HTTPS proxy server is used to route traffic from the intranet to the Internet, the network proxy must be configured in the Web Console under Technician Console, Network Configuration.
Chapter 2. CPU Features & Specifications Configure Time Synchronization In order for industrial data time-stamping and Field Agent diagnostic information to operate reliably, it is important for the Field Agent to have an accurate time source. The Field Agent has two methods of synchronizing time –...
Note that communications between the CPE400 and the Predix Cloud is secured using authentication and encryption. Note that the Field Agent firmware within the CPE400 may need to be updated from time to time. GE recommends that all such firmware be kept up-to-date. The Technician has the ability to configure the Field Agent for scheduled automatic updates or manual updates.
Chapter 2. CPU Features & Specifications Ethernet Indicators (EFA RJ45 Built-in LEDs) Two LEDs are integrated into the EFA RJ45 connector. These LEDs indicate the link status and link speed, as follows: LED State Operating State Link On Green The corresponding link has been established. Status Blinking Traffic is detected at the corresponding port.
Chapter 2. CPU Features & Specifications Hot Standby Redundancy With firmware version 9.30 or later, it is possible to configure the CPE400 as a Hot Standby Redundancy CPU with PROFINET IO. The two ports on LAN3 are used exclusively for this purpose: they provide a high- speed data synchronization link between the two CPUs.
Chapter 2. CPU Features & Specifications Redundant IP Addresses Effective with firmware version 9.30, the CPE400 supports two independent Redundant IP addresses, one for LAN1 and one for LAN2. LAN2 Redundant IP is supported when configured for Ethernet mode only. Redundant IP is supported by the SRTP Server, Modbus TCP Server, and EGD protocols.
Chapter 2. CPU Features & Specifications Display Port The Display port is not functional at time of publication. The Display Port is a DP++ video port located on the underside of the CPE440 (Figure 3). It provides signals for connecting a suitable monitor or video adapter. Pinouts for the Display Port (Figure 14) are: Pins Signal Name TxD0+/-...
Chapter 2. CPU Features & Specifications Energy Pack Connector The CPE400 compatible Energy Pack, IC695ACC403, is supplied with a purpose-built cable which installs in the connector shown in Figure 3. Use of the Energy Pack is optional. Once charged up, the ACC403 allows the CPE400 to instantly save user memory to non-volatile storage in the event of loss of power.
4. Take the CPE400 to a clean environment. 5. Remove the DIN-rail or panel-mount adaptor plate, as applicable. 6. Place the CPE400 on a workbench so that the heat-sink adjacent to the GE logo on the front panel is facing up.
21. Turn power back on. 22. If needed, set the current date and time via Proficy Machine Edition. The replacement battery must be IC690ACC001 from GE Automation & Controls, or an equivalent, such as Rayovac™ Lithium BR2032 Coin Cell 3V 190mAh -40°C to +85°C.
Chapter 2. CPU Features & Specifications Setting the CPE400’s Real-Time Clock The CPE400’s Real-Time Clock may be set by both the PACSystems Runtime and the Field Agent: • The clock may be set from PACSystems using utilities in Proficy Machine Edition. •...
Chapter 2. CPU Features & Specifications Replacement of CPE400 Mounting Bracket When shipped, the CPE400 is attached to the DIN-rail mounting bracket. The panel-mount bracket is supplied in the shipping carton, unattached. If the application requires panel-mounting rather than DIN- Rail mounting, exchange the mounting brackets, as follows.
Chapter 2. CPU Features & Specifications 2.2.2 CPE330 Figure 18: CPE330 Front View & Features GFK-2222AD April 2018...
Any of the embedded Ethernet ports may be used to communicate with the Proficy Machine Edition (PME) programming and configuration software using the Service Request Transport Protocol (SRTP, a proprietary GE protocol, used primarily for communication with the programmer). For default IP Address and other details, refer to Establishing Initial Ethernet Communications, Section 3.4.1.
Chapter 2. CPU Features & Specifications Switches CPE330 The RDSD and RUN/STOP Switches are located behind the protective door, as shown in Figure 19. Refer to RUN/STOP Switch Operation in Chapter 4. The Reset pushbutton, located just above these switches, is currently not used.
Chapter 2. CPU Features & Specifications Indicators CPE330 Blinking CPU Status Indicators CPE330 LED State Operating State CPU OK CPU has passed its power-up diagnostics and is functioning On Green properly. (After initialization sequence is complete.) Power is not applied or CPU has a problem, which may be indicated by blink pattern.
Chapter 2. CPU Features & Specifications Blinking Ethernet Indicators CPE330 (embedded in RJ45 connectors) LED State Operating State LINK (upper) On Green The corresponding link is physically connected. Blinking Green Traffic is detected at the corresponding port. No connection detected at the corresponding port. 1Gbps (lower) On Amber (LAN1) Corresponding network data speed is 1 Gbps.
15. Reconnect all cables to their original connectors. 16. Turn power on to the RX3i rack. 17. If needed, set the current date and time via PME or using SVC_REQ 7 (refer to PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 6).
Chapter 2. CPU Features & Specifications Replacement Real-Time Clock Battery The replacement battery must be IC690ACC001 from GE Automation & Controls, or an equivalent, such as Rayovac™ Lithium BR2032 Coin Cell 3V 190mAh -40°C to +85°C. Warning Use of a different type of battery than that specified here may present a risk of fire or explosion.
Chapter 2. CPU Features & Specifications Backwards Compatibility of CPE330 with CPU320, CRU320, or CPU315 The CPE330 may be interchanged with a corresponding CPU320/CRU320 with no upgrade to Proficy Machine Edition (PME) software. Logic and configuration equality in PME are maintained when storing the same project to either a CPU320/CRU320 or a CPE330.
Chapter 2. CPU Features & Specifications When the desired compatibility setting is displayed, press the RDSD UPLD button to save the setting and allow the CPE330 to continue its normal startup procedures with the new setting. The setting is maintained over a power cycle and firmware upgrade. Note that with versions of PME that do not have native CPE330 support, only CPU320 projects can be stored to a CPE330 that is in CPU320 compatibility mode.
Chapter 2. CPU Features & Specifications 2.2.3 CPE302, CPE305 and CPE310 Figure 21: IC695CPE302/CPE305 Front Figure 22: IC695CPE310 Front View View PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD...
Chapter 2. CPU Features & Specifications Serial Ports These ports provide serial interfaces to external devices and can be used for firmware upgrades. For serial port pin assignments, electrical isolation, and details on serial communications, refer to Chapter 5. CPE302/CPE305: one RS-232 port (using RJ-25 connector).
Chapter 2. CPU Features & Specifications Switches CPE302/CPE305 & CPE310 The RDSD and RUN/STOP Switches are located behind the protective door, as shown in Figure 23 and Figure 24. Refer to RUN/STOP Switch Operation in Chapter 4. The Reset pushbutton is not used. Figure 23: External Features of CPE302/CPE305 Figure 24: External Features of CPE310 RDSD Switch Operation CPE302/CPE305 &...
Chapter 2. CPU Features & Specifications Indicators CPE302/CPE305 & CPE310 Blinking CPU Indicators CPE302/ CPE310 LED LED State CPU Operating State CPE305 LED CPU OK CPU has passed its power-up diagnostics and is functioning On Green properly. (After initialization sequence is complete.) CPU problem.
Chapter 2. CPU Features & Specifications Blinking RDSD Indicators CPE302/CPE305 & CPE310 CPE302/ CPE310 LED LED State RDSD Operating State CPE305 LED SYS FLT The RDSD has been removed during a store. The On Red CPU must be power cycled to resume RDSD RDSD / COM2 Off or operations.
Figure 25: Accessing Real-Time Clock Battery (CPE302, CPE305 and CPE310) Replacing the Real-Time Clock Battery in CPE302/CPE305/CPE310 The replacement battery must be IC690ACC001 from GE Automation & Controls, or an equivalent, such as Rayovac Lithium BR2032 Coin Cell 3V 190mAh -40°C to +85°C. Warning Use of a different type of battery than that specified here may present a risk of fire or explosion.
Chapter 2. CPU Features & Specifications Battery Removal Method 1 1. Power down the rack and remove the CPU from the backplane. 2. Using a curved probe with a non-conducting surface, for example a non-metallic dental pick, reach in from the back of the module and pull the battery out of its retaining clip. (You can use needle-nose pliers to grasp the battery and pull it the rest of the way out.) Sample Tool for Battery Removal Figure 26: Sample Tool for Coin Battery Extraction...
Chapter 2. CPU Features & Specifications Backwards Compatibility of CPE310 with CPU310 The CPE310 may be swapped with a CPU310 with no upgrade to the Proficy Machine Edition Logic Developer-PLC programming software. Logic and configuration equality in the programming software is maintained when storing the same project to either a CPU310 or a CPE310.
Chapter 2. CPU Features & Specifications CPE310 versus CPU310 Performance Differences The following differences should be considered when converting legacy applications or developing new applications. ▪ Some exceptionally lengthy CPE backplane operations, such as MC_CamTableSelect, Data Log and Read Event Queue functions, will take longer to complete compared to other RX3i CPU models, and may delay backplane operations to IC695 modules.
Chapter 2. CPU Features & Specifications 2.2.4 CPU315 and CPU320/CRU320 Figure 27: IC695CPU320 Front View Serial Ports CPU315, CPU320 & CRU320 Each CPU has two independent, on-board serial ports, accessed by connectors on the front of the module. COM1 and COM2 provide serial interfaces to external devices. Either port can be used for firmware upgrades.
Chapter 2. CPU Features & Specifications Indicators CPU315, CPU320 & CRU320 Eight CPU LEDs indicate the operating status of various CPU functions. Two Comm LEDs indicate activity on COM1 and COM2. LED State CPU Operating State Blinking CPU OK CPU has passed its power-up diagnostics and is On Green functioning properly.
Chapter 2. CPU Features & Specifications Error Checking and Correction, IC695CRU320 RX3i Redundancy CPUs provide error checking and correction (ECC), which results in slightly slower system performance, primarily during power-up, because it uses an extra 8 bits that must be initialized. For details on ECC, refer to the PACSystems Hot Standby CPU Redundancy User Manual, GFK-2308.
Chapter 2. CPU Features & Specifications 2.2.5 CPU310 Figure 28: IC695CPU310 Front View Serial PortsCPU310 The CPU has two independent, on-board serial ports, accessed by connectors on the front of the module. COM1 and COM2 provide serial interfaces to external devices. Either port can be used for firmware upgrades.
Chapter 2. CPU Features & Specifications Indicators CPU310 The eight CPU LEDs indicate the operating status of various CPU functions. The two Comm LEDs indicate activity on COM1 and COM2. CPU Operating State Blinking LED State CPU OK CPU has passed its power-up diagnostics and is On Green functioning properly.
Chapter 2. CPU Features & Specifications CPE010 CPE020 CPE030 CPE040 Time-of-Day Clock Time-of-Day Clock Accuracy (@60°C) ±9 secs/day ±9 secs/day ±2 secs/day ±2 secs/day Elapsed Time Clock (internal timing) accuracy ±0.01% max ±0.01% max ±0.01% max ±0.01% max Simple Network Time Protocol (SNTP) accuracy to timestamp ±2 ms ±2 ms ±2 ms...
Chapter 2. CPU Features & Specifications 2.3.1 CPE030/CRE030 and CPE040/CRE040 Serial Ports CPE030/CRE030 & CPE040/CRE040 Each CPU has three independent, on-board serial ports, accessed by connectors on the front of the module. COM1 and COM2 provide serial interfaces to external devices;...
Chapter 2. CPU Features & Specifications Error Checking and Correction, IC698CRE030 and IC698CRE040 Redundancy CPUs are shipped with error checking and correction (ECC) enabled. Enabling ECC results in slightly slower system performance, primarily during power-up, because it uses an extra eight bits that must be initialized.
Chapter 2. CPU Features & Specifications 2.3.2 CPE010, CPE020 and CRE020 Serial Ports CPE010, CPE020 & CRE020 Each CPU has three independent, on-board serial ports, accessed by connectors on the front of the module. COM1 and COM2 provide serial interfaces to external devices; either can be used for firmware upgrades.
Chapter 2. CPU Features & Specifications Error Checking and Correction, IC698CRE020 Redundancy CPUs are shipped with error checking and correction (ECC) enabled. Enabling ECC results in slightly slower system performance, primarily during power-up, because it uses an extra eight bits that must be initialized.
Chapter 2. CPU Features & Specifications 2.3.3 RX7i Embedded Ethernet Interface Ethernet Ports The RX7i embedded Ethernet Interface provides two RJ45 Ethernet ports. Either or both of these ports may be connected to other Ethernet devices. Each port automatically senses the data rate (10 Mbps or 100 Mbps), communication mode (half-duplex or full-duplex), and cabling arrangement (straight-through or crossover) of the attached link.
Chapter 2. CPU Features & Specifications Ethernet LED Operation LED State Ethernet Operating State Blinking Blink error code Hardware Failure STAT Fast Blink Performing Diagnostics STAT Slow Blink Waiting for Ethernet configuration from CPU STAT † Slow Blink Waiting for IP Address On/Traffic/Off †...
Chapter 2. CPU Features & Specifications EOK LED Operation The EOK LED indicates whether the Ethernet interface is able to perform normal operation. This LED is on for normal operation and blinks for all other operations. When a hardware or unrecoverable runtime failure occurs, the EOK LED blinks a two-digit error code identifying the failure.
Chapter 2. CPU Features & Specifications LAN LED Operation The LAN LED indicates access to the Ethernet network. During normal operation, and while waiting for an IP address, the LAN LED blinks to indicate network activity. This LED remains on when the Ethernet interface is not actively accessing the network but the network is available, and it is off if network access is not available.
Chapter 2. CPU Features & Specifications Ethernet Restart Pushbutton The Ethernet Restart pushbutton is used to manually restart the Ethernet firmware without power cycling the entire control system. It is recessed to prevent accidental operation. The restart does not occur until the pushbutton is released. The type of restart behavior is selected by the length of time that the pushbutton is depressed.
Chapter 2. CPU Features & Specifications RSTi-EP CPU Features and Specifications CPE100/CPE115 Lifecycle Phase Active 1GHz TI AM335x Microprocessor Specification Sitara SoC Operating System VxWorks #RX3i Slots Occupied Backplane Standalone Temperature Range RSTi-EP -40°C to 70°C Power Requirements RSTi-EP +3.3Vdc RSTi-EP +5 Vdc RSTi-EP +24Vdc Relay with Energy Pack RSTi-EP +24Vdc Relay w/o Energy Pack...
Note: Whenever the size of any reference memory is changed, the content of the corresponding reference memory is automatically cleared. For discussion of memory types and how they are managed, refer to PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter 3.
Chapter 2. CPU Features & Specifications CPE100/CPE115 Protocols Modbus RTU Slave SNP Slave Serial I/O SRTP (# simultaneous server conns) up to 16 Modbus TCP up to 8 (# simultaneous server connections) SRTP Channel or Modbus TCP Client up to 8 (# simultaneous) Ethernet Global Data (EGD) Number of EGD Exchanges (max)
Chapter 2. CPU Features & Specifications 2.4.1 CPE100/CPE115 Introduction The EPSCPE100 and EPSCPE115 are the first standalone CPUs in the RSTi-EP family. Each is supported by two mounting options: 1) As shipped, it mounts onto a DIN rail using a DIN-rail adaptor plate. 2) Alternately, it mounts directly in a cabinet, using a panel-mount adaptor plate ICMFAACC001- The mounting instructions and power requirements are documented in the Quick Start Guide, GFK-3012, and are not replicated here.
Chapter 2. CPU Features & Specifications The CPE100/CPE115 are programmed and configured over Ethernet via GE’s Proficy* Machine Edition (PME) software. Each is a standalone CPU with the following features: • A built-in PACSystems RSTi-EP PLC CPU o User may program in Ladder Diagram, Structured Text, Function Block Diagram.
Chapter 2. CPU Features & Specifications Membrane Run/Stop Pushbutton Figure 32: CPE100/CPE115 Membrane Pushbutton and Module Status LEDs If the blue membrane pushbutton (Figure 32) is pressed while the CPE100/CPE115 is powering up, it restores the default IP address (192.168.0.100). It also erases the stored hardware configuration, logic and contents of the backup RAM.
Chapter 2. CPU Features & Specifications LED Indicators (LEDs) Ethernet Status Indicators There are two LEDs (Yellow/Green) for each Ethernet ports of LAN1 and LAN2, which are embedded in the RJ45 connectors. The green LED indicates an Ethernet connection has been established. The yellow LED indicates packet traffic.
Chapter 2. CPU Features & Specifications Ethernet Ports CPE100/CPE115 provides two independent Fast Ethernet LANs. LAN1 has only one port and is dedicated to embedded Ethernet controller and whereas LAN2 is comprised of 3 switched ports configurable either as a second embedded Ethernet controller or as an embedded PROFINET controller. All the Ethernet ports of both the LAN1 and LAN2 are capable of automatically sensing the link data rate (10 Mbps or 100 Mbps), communications mode (half-duplex or full-duplex), and cabling arrangement (straight-through or crossover).
Chapter 2. CPU Features & Specifications Ethernet Topology A typical application will take advantage of the two independent LANs. The dedicated LAN1 port will be used for communications with plant-level or supervisory layers. The switched LAN2 will be used to communicate with devices over PROFINET within the manufacturing cell or process.
Chapter 2. CPU Features & Specifications Super Capacitor In the event of loss of system power, the internal super capacitor maintains power long enough for the CPE100/CPE115 to write its user memory contents to non-volatile storage (flash) memory. Operation When the CPE100/CPE115 is powered up for the first time, or is in a system that has been powered down long enough to completely discharge the internal super capacitor, it may additional require 70 to 75 seconds for it to charge to its operating level.
Chapter 3 CPU Configuration The PACSystems CPU and I/O system is configured using Proficy Machine Edition (PME) Logic Developer- PLC programming software. The CPU verifies the physical module and rack configuration at power-up and periodically during operation. The physical configuration must be the same as the programmed configuration. Differences are reported to the CPU alarm processor for configured fault response.
Chapter 3. CPU Configuration Configuring the CPU To configure the CPU using the Logic Developer-PLC programming software, do the following: In the Project tab of the Navigator, expand your PACSystems Target, the hardware configuration, and the main rack (Rack 0). Right click the CPU slot and choose Configure.
Configuration Parameters 3.2.1 Settings Parameters These parameters specify basic operating characteristics of the CPU. For details on how these parameters affect CPU operation, refer to PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter 2. Settings Parameters Passwords Specifies whether passwords are Enabled or Disabled.
Chapter 3. CPU Configuration Settings Parameters RUN/STOP Enables or disables the physical operation of the RUN/STOP Switch. Switch Choices: Enabled: Enables you to use the physical switch on the PLC to switch the PLC into STOP Mode or from STOP Mode into RUN Mode and clear non-fatal faults. Disabled: Disables the physical RUN/STOP Switch on the PLC.
Chapter 3. CPU Configuration Settings Parameters LAN1 Mode RX3i CPE330/CPE400 and RSTi-EP CPE100/CPE115 CPUs only. CPU LAN1 port mode. Choices: Ethernet: LAN port 1 is used for Ethernet communications. Default: Ethernet. LAN2 Mode RX3i CPE330/CPE400 and RSTi-EP CPE100/CPE115 CPUs only. CPU LAN2 port mode. Choices: Ethernet: LAN port 2 is used for Ethernet communications.
Chapter 3. CPU Configuration Settings Parameters Day Light RX3i CPE302/CPE305/CPE310/CPE330/CPE400 CPUs only. Activates Day Light Savings Savings Time Time (DST) settings for the controller. Allows you to select appropriate local start and end (DST) times for Day Light Savings Time. Choices: Disabled: Day Light Savings Time settings are not active.
Chapter 3. CPU Configuration 3.2.3 SNTP This tab displays the Simple Network Time Protocol configuration settings when SNTP is active. SNTP Mode SNTP Mode of operation. Specify the use of Multicast/Broadcast or Unicast settings to communicate to the time server. Choices: Multicast/Broadcast or Unicast.
Chapter 3. CPU Configuration 3.2.4 Time This tab displays the Coordinated Universal Time (UTC) and Day Light Savings Time (DST) configuration settings when UTC or DST are active. UTC Offset Local time zone offset with respect to UTC time. Valid Range: Select the closest appropriate time zone for your location. Default: [UTC-5] Eastern Standard Time.
Chapter 3. CPU Configuration 3.2.5 Scan Parameters These parameters determine the characteristics of CPU sweep execution. Scan Parameters Sweep Mode The sweep mode determines the priority of tasks the CPU performs during the sweep and defines how much time is allotted to each task. The parameters that can be modified vary depending on the selection for sweep mode.
Chapter 3. CPU Configuration Scan Parameters Controller (Available only when Sweep Mode is set to Normal. Read-only if the Controller Communications Communications Window Mode is set to Complete.) The maximum execution time for the Window Timer Controller Communications Window per scan. This value cannot be greater than the value (ms) for the watchdog timer.
Chapter 3. CPU Configuration Scan Parameters Window Timer (Available only when Sweep Mode is set to Constant Window.) The maximum combined (ms) execution time per scan for the Controller Communications Window, Backplane Communications Window, and Background Communications Window. This value cannot be greater than the value for the watchdog timer.
For details on using symbolic variables and I/O variables, refer to PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter 4.
Chapter 3. CPU Configuration Memory Allocation Configuration Memory Parameters Reference Points %I Discrete Input, %Q Discrete The upper limit for the range of each of these memory types. Read only. Output, %M Internal Discrete, %S System, %SA System, %SB System, %SC System, %T Temporary Status, %G Genius Global Total Reference Points...
Chapter 3. CPU Configuration Memory Parameters Point Fault References The Point Fault References parameter must be enabled if you want to use fault contacts in your logic. Assigning point fault references causes the CPU to reserve additional memory. When you download both the HWC and the logic to the PLC, the download routine checks if there are fault contacts in the logic and if there are, it checks if the HWC to download has the Point Fault References parameter set to Enabled.
Chapter 3. CPU Configuration 3.2.7 Fault Parameters You can configure each fault action to be either diagnostic or fatal. A diagnostic fault does not stop the PLC from executing logic. It sets a diagnostic variable and is logged in a fault table. A fatal fault transitions the PLC to the Stop Faulted mode.
Exchange Status Words to determine the health of individual EGD exchanges. For details on this status word, refer to Exchange Status Word Error Codes in PACSystems RX7i, RX3i and RSTi-EP TCP/IP Ethernet Communications User Manual, GFK-2224. Because the types of errors indicated by the exchange status word may be temporary in nature, stopping the CPU may not be an appropriate response for these errors.
Chapter 3. CPU Configuration 3.2.8 Redundancy Parameters (Redundancy CPUs Only) These parameters apply only to redundancy CPUs or to those CPUs where the optional redundancy features have been activated. For details on configuring CPU for redundancy, refer to the PACSystems Hot Standby CPU Redundancy User Manual, GFK-2308.
Chapter 3. CPU Configuration 3.2.10 COM1 and COM2 Parameters These parameters configure the operating characteristics of the CPU serial ports . COM1 and COM2 have the same set of configuration parameters. The protocol (Port Mode) determines the parameters that can be set for each port. Port Parameters Port Mode The protocol to execute on the serial port.
Chapter 3. CPU Configuration Port Parameters Data Rate (All Port Modes, except Available.) Data rate (bits per second) for the port. Choices: 1200 Baud, 2400 Baud, 4800 Baud, 9600 Baud, 19.2k Baud, 38.4k Baud, 57.6k Baud, 115.2k Baud. Default: 19.2k Baud. Data Bits (Available only when Port Mode is set to Message mode or Serial I/O.) The number of bits in a word for serial communication.
Chapter 3. CPU Configuration Port Parameters SNP ID (Available only when Port Mode is set to SNP Slave.) The port ID to be used for SNP communications. In SNP multi-drop communications, this ID is used to identify the intended receiver of a message. This parameter can be left blank if communication is point to point. To change the SNP ID, click the values field and enter the new ID.
Chapter 3. CPU Configuration Port Parameters Timeout(s) (Available only when STOP Mode is set to SNP Slave.) The maximum time that the slave will wait to receive a message from the master. If a message is not received within this timeout interval, the slave will assume that communications have been disrupted, and then it will wait for a new attach message from the master.
Chapter 3. CPU Configuration 3.2.11 Scan Sets Parameters You can create multiple sets of asynchronous I/O scans, with a unique scan rate assigned to each scan set. You can assign up to 31 scan sets for a total of 32. Scan set 1 is the standard scan set where I/O is scanned once per sweep.
Chapter 3. CPU Configuration 3.2.13 Access Control The Access Control List allows you to specify the reference address ranges that can be accessed by non-local devices such as HMIs and other controllers. To use this feature, Enhanced Security must be enabled in the properties of the target.
Chapter 3. CPU Configuration 3.2.14 OPC UA Parameters These parameters enable or disable the OPC UA Server. OPC UA Parameters Server Specify whether the CPU’s OPC UA Server is enabled or not. Enabled Valid Range: True or False. Default: True. UTC Offset Local time zone offset with respect to UTC time.
Chapter 3. CPU Configuration Storing (Downloading) Hardware Configuration A PACSystems control system is configured by creating a configuration file using the PME programming and configuration software, then transferring (downloading) the file from the programmer to the CPU via serial port COM1, serial port COM2, or via an Ethernet port. If you use a serial port, it must be configured as RTU Slave (default) or SNP Slave.
Figure 38: Selecting Embedded Ethernet for Configuration Ethernet interface configuration includes the following additional procedures. For details on completing these steps, refer to the PACSystems RX7i, RX3i and RSTi-EP TCP/IP Ethernet Communications User Manual, GFK-2224. ▪ Assigning an IP Address for initial network operation, such as connecting the programmer to download the hardware configuration, using the Set Temporary IP Address utility (refer to Setting a Temporary IP Address) or by downloading a hardware configuration through a serial connection.
Chapter 3. CPU Configuration 3.4.1 Establishing Initial Ethernet Communications To establish Ethernet communications between the PME programming and configuration software and the CPU, you first need to set an IP address. Use one of the following methods: Default IP Addresses for RX3i Initial Ethernet communication with the CPU may be established CPE302/CPE305/CPE310/CPE330/ using the default IP addresses programmed at the factory:...
Chapter 3. CPU Configuration Connecting to RSTi-EP CPE100/CPE115 The default IP address (192.168.0.100) of CPE100/CPE115 can be Embedded Ethernet when IP Addresses restored by powering up the module with the pushbutton pressed are not known and waiting until the OK LED flashes twice. Note: Setting a Temporary IP Address tool is not available for CPE100/CPE115.
Chapter 3. CPU Configuration 3.4.2 Setting a Temporary IP Address If supported by the host CPU , use the Set Temporary IP Address utility to specify an IP address in place of one that has been lost or forgotten. The following restrictions apply when using the Set Temporary IP Address utility: ▪...
Chapter 3. CPU Configuration Caution The temporary IP Address set by the Set Temporary IP Address utility is not retained through a power cycle. To set a permanent IP Address, you must set the IP Address property of the target and download (store) HWC to the PACSystems. The Set Temporary IP Address utility can assign a temporary IP Address even if the target Ethernet Interface has previously been configured to a non-default IP Address.
Chapter 4 CPU Operation This chapter describes the operating modes of a PACSystems CPU and describes the tasks the CPU carries out during these modes. The following topics are discussed: ■ CPU Sweep ■ Program Scheduling Modes ■ Window Modes ■...
Chapter 4. CPU Operation CPU Sweep The application program in the CPU executes repeatedly until stopped by a command from the programmer, from another device, from the RUN/STOP Switch on the CPU module, or a fatal fault occurs. In addition to executing the application program, the CPU obtains data from input devices, sends data to output devices, performs internal housekeeping, performs communications tasks, and performs self- tests.
Chapter 4. CPU Operation 4.1.1 Parts of the CPU Sweep There are seven major phases in a typical CPU sweep as shown in the following figure. Housekeeping Start-of-Sweep input scan Application Program Task Execution (Logicwindow) WINDOW) Output Scan Prog window scheduled Controller Communications...
(Logic Window) For details on controlling the execution of programs, refer to PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter 2. Interrupt driven logic can execute during any phase of the sweep. For details, refer to PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter...
Chapter 4. CPU Operation Phase Activity Controller Services the onboard Ethernet and serial ports. In addition, reconfiguration of expansion Communications racks and individual modules occurs during this portion of the sweep. Window The CPU always executes this window. The following items are serviced in this window: ▪...
Chapter 4. CPU Operation 4.1.2 CPU Sweep Modes Normal Sweep Mode In Normal Sweep mode, each sweep can consume a variable amount of time. The Logic window is executed in its entirety each sweep. The Communications windows can be set to execute in a Limited or Run-to-Completion mode.
Chapter 4. CPU Operation Constant Sweep Mode In Constant Sweep mode, each sweep begins at a specified Constant Sweep time after the previous sweep began. The Logic Window is executed in its entirety each sweep. If there is sufficient time at the end of the sweep, the CPU alternates among the Controller Communications, Backplane Communications, and Background Windows, allowing them to execute until it is time for the next sweep to begin.
Chapter 4. CPU Operation Constant Window Mode In Constant Window mode, each sweep can consume a variable amount of time. The Logic Window is executed in its entirety each sweep. The CPU alternates among the three windows, allowing them to execute for a time equal to the value set for the Constant Window timer.
Chapter 4. CPU Operation Window Modes The previous section describes the phases of a typical CPU sweep. The Controller Communications, Backplane Communications, and Background windows can be run in various modes, based on the CPU sweep mode. (Refer to CPU Sweep Modes.) The following three window modes are available: Run-to- In Run-to-Completion mode, all requests made when the window has started are Completion...
Chapter 4. CPU Operation Data Coherency in Communications Windows When running in Constant or Limited Window mode, the Controller and Backplane Communications Windows may be terminated early in all CPU sweep modes. If an external device, such as CIMPLICITY HMI, is transferring a block of data, the coherency of the data block may be disrupted if the communications window is terminated prior to completing the request.
Chapter 4. CPU Operation Run/Stop Operations The PACSystems CPUs support four RUN/STOP Modes of operation. You can change these modes in the following ways: the RUN/STOP Switch, configuration from the programming software, LD function blocks, and system calls from C applications. Switching to and from various modes can be restricted based on privilege levels, position of the RUN/STOP Switch, passwords, etc.
Chapter 4. CPU Operation 4.5.1 CPU STOP Modes The CPU has four modes of operation while it is in STOP Mode. The two most common are: STOP-I/O Enabled Mode ▪ I/O Scan Enabled - the Input and Output scans are performed each sweep. STOP-I/O Disabled Mode ▪...
The PACS Analyzer software is a tool that is embedded in PME. It can also be downloaded from the GE Automation and Controls support website www.geautomation.com. If backplane communications have been suspended, the PACS Analyzer must be directly connected to a serial or Ethernet port on the CPU.
The Read Switch Position (Switch_Pos) function allows the logic to read the current position of the RUN/STOP Switch, as well as the mode for which the switch is configured. For details, refer to PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter 4. PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual...
Chapter 4. CPU Operation Flash Memory Operation The CPU stores the current configuration and application in user memory (either battery-backed RAM or non-volatile user memory, depending on the CPU model). You can also store the Logic, Hardware Configuration, and Reference Data into non-volatile flash memory. The PACSystems CPU provides enough flash memory to hold all of user space, all reference tables that aren't counted against user space, and any overhead required.
Chapter 4. CPU Operation Logic/Configuration Source and CPU Operating Mode at Power-Up Flash and user memory can contain different values for the Logic/Configuration Power-up Source parameter. The following tables summarize how these settings determine the logic/configuration source after a power cycle. CPU mode is affected by the Power-up Mode, the RUN/STOP Switch and Stop-Mode I/O Scanning parameters, the physical RUN/STOP Mode Switch position, and the Power Down Mode as shown in sections 4.7.1 and 4.7.2.
Chapter 4. CPU Operation 4.7.1 CPU Mode when Memory Not Preserved/Power-up Source is Flash Configuration Parameters RUN/STOP Switch Position CPU Mode Power-up Mode RUN/STOP Switch Enabled Stop Stop Disabled Enabled Run Disabled Run Disabled Enabled Run Enabled Run Enabled Disabled Run Disabled Stop Stop Disabled...
Chapter 4. CPU Operation 4.7.2 CPU Mode when Memory Preserved Configuration Parameters RUN/STOP Power Down CPU Mode Power-up RUN/STOP Stop-Mode I/O Switch Position Mode Mode Switch Scanning Enabled Enabled Stop Stop Enabled Enabled Disabled Stop Stop Disabled Enabled Run Disabled Run Disabled Enabled Run Enabled...
For information on timer functions and timed contacts provided by the CPU instruction set, refer to Timers in PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter 4.8.1 Elapsed Time Clock The elapsed time clock tracks the time elapsed since the CPU powered on. The clock is not retentive across a power failure;...
2036. You can read and set the hardware TOD time and date through the application program using Service Request function #7. For details, refer to PACSystems RX7i, RX3i and RSTi-EP CPU Programmer’s Reference Manual, GFK-2950 Chapter 6.
Chapter 4. CPU Operation 4.8.3 Watchdog Timer Software Watchdog Timer A software watchdog timer in the CPU is designed to detect failure to complete sweep conditions. The timer value for the software watchdog timer is set by using the programming software. The allowable range for this timer is 10 ms to 2550 ms;...
Analyzer to view the fault tables, including any faults logged before the timeout. (See below for distinctions between CPU and CPE behavior.) The PACS Analyzer software is a tool that is embedded in PME. It can also be downloaded from GE’s Automation and Controls support website www.geautomation.com/support.
Chapter 4. CPU Operation System Security The PACSystems CPU supports two types of system security: ▪ Passwords/privilege levels ▪ OEM protection CPU versions 7.80 and later support Enhanced Security (including merged password tables). This provides a more secure mechanism for setting and authenticating passwords and OEM keys versus the Legacy Security Mode.
Chapter 4. CPU Operation 4.9.1 Passwords and Privilege Levels - Legacy Mode Passwords are a configurable feature of the PACSystems CPU. Their use is optional and is set up using the programming software. Passwords provide different levels of access privilege for the CPU when the programmer is Online.
Chapter 4. CPU Operation Maintaining Passwords through a Power Cycle Initial passwords are blank for a new controller or a controller that has its passwords cleared. For passwords to be maintained through power cycles, the controller must either: Store to RAM and use an Energy Pack or battery to maintain memory. Store to User Flash with configuration set up to load from Flash at power up.
Chapter 4. CPU Operation 4.9.2 OEM Protection – Legacy Mode Original Equipment Manufacturer (OEM) protection provides a higher level of security than password levels 1 through 4. This feature allows a third-party OEM to create control programs for the CPU and then set the OEM-locked mode, which prevents the end user from reading or modifying the program.
Chapter 4. CPU Operation 4.9.3 Enhanced Security for Passwords and OEM Protection Enhanced Security passwords are supported by CPU firmware versions 7.80 or later. This feature provides a cryptographically secure password protocol between an SRTP client (for example Proficy Machine Edition) and a PACSystems controller. Enhanced Security passwords operate in a very similar fashion to the Legacy security password operation that is supported by previous firmware versions.
Chapter 4. CPU Operation 4.9.4 Legacy/Enhanced Security Comparison Feature Legacy (less secure) Enhanced (more secure) Level 2, 3 and 4 protection Levels 2, 3 and 4 must be set or modified Passwords can be set individually or simultaneously. (If you only want to group.
Chapter 4. CPU Operation 4.10 PACSystems I/O System The PACSystems I/O system provides the interface between the CPU and other devices. The PACSystems I/O system supports: ▪ I/O and Intelligent option modules. ▪ Ethernet Interface ▪ Motion modules (RX3i) ▪ PROFINET: RX3i CPE330, CPE400 and RSTi-EP CPE100/CPE115 all permit one of their LANs to be configured as an embedded PROFINET Controller (see Section 2.1.6, Embedded PROFINET Controller).
Chapter 4. CPU Operation 4.10.1 I/O Configuration Module Identification In addition to the catalog number, the programming software stores a Module ID for each configured module in the hardware configuration that it delivers to the CPU. The CPU uses the Module ID to determine how to communicate with a given module.
Chapter 4. CPU Operation Default Conditions for I/O Modules Interrupts Some input modules can be configured to send an interrupt to the application program. By default, this interrupt is disabled and the input filter is set to slow. If changed by the programming software, the new settings are applied when the configuration is stored and during subsequent power-cycles.
In the I/O Fault Table, the rack, slot, bus, module, and I/O point number are given for a fault. Refer to PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 9 for decoding. In non-redundant systems, bus #1 refers to the bus on the single-channel GBC. In redundant systems, bus number is represented as either #1 or #2.
Chapter 4. CPU Operation Genius Global Data Communications The PACSystems RX7i supports the sharing of data among multiple control systems that share a common Genius I/O bus. This mechanism provides a means for the automatic and repeated transfer of %G, %I, %Q, %AI, %AQ, %R, and %W data. No special application programming is required to use global data since it is integrated into the I/O scan.
Chapter 4. CPU Operation 4.10.3 I/O System Diagnostic Data Collection Diagnostic data in a PACSystems I/O system is obtained in either of the following two ways: ▪ If an I/O module has an associated bus controller, the bus controller provides the diagnostic data from that module to the CPU.
Chapter 4. CPU Operation PACSystems Handling of GBC Faults Defaulting of input data associated with failed/lost GBCs When a GBC is missing, mismatched, or otherwise failed, the CPU applies the Input Default setting for each device on that Genius bus when defaulting the input data. If the device is configured for HOLD LAST STATE, the data is left alone.
Chapter 4. CPU Operation 4.11 Power-Up and Power-Down Sequences 4.11.1 Power-Up Sequence System power-up consists of the following parts: ▪ Power-up self-test ▪ CPU memory validation ▪ System configuration ▪ Intelligent option module self-test completion ▪ Intelligent option module dual port interface tests ▪...
Chapter 4. CPU Operation Intelligent Option Module Self-Test Completion Intelligent option modules may take a longer time to complete their self-tests than the CPU due to the time required to test communications media or other interface devices. As an intelligent option module completes its initial self-tests, it tells the CPU the time required to complete the remainder of these self- tests.
Chapter 4. CPU Operation 4.11.3 Power Cycle Operation with an Energy Pack Energy Packs offer distinct advantages over batteries: a) significantly longer life cycles b) they are more reliable c) flammability during shipment is not an issue d) in their end-of-life phase, their decline is a lot more gradual. The system design includes the ability of the CPU and the Energy Pack to monitor each other in real time.
As shown in the table below, the CPU application program can monitor the status of the attached Energy Pack via %S0014 (PLC_BAT) and %SA0011 (LOW_BAT). For more details, refer to the chapter on Diagnostics in PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950. PLC_BAT...
Chapter 4. CPU Operation CPE400/ACC403 Status Detection & Fault Reporting Both the CPE400 and ACC403 contain intelligence, allowing each to determine the status of the other. This permits the CPU to report various conditions to the user via the status bits discussed in Energy Pack Status Bit Operation.
Chapter 4. CPU Operation 4.11.4 Retention of Data Memory Across Power Failure The following types of data are preserved across a power cycle with an operational battery (for RX3i CPE302, CPE305, CPE310, CPE330),CPE400 models with an operational and attached Energy Pack. RSTi- EP CPE100/CPE115 have in built super capacitor for data retention.
This chapter describes the Ethernet and Serial communications features of the PACSystems CPU. Ethernet communications may be handled by the embedded CPU Ethernet port(s) or by an IC695ETM001 module installed in an RX3i rack. Refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual, GFK-2224.
Chapter 5. Communications Ethernet Communications For details on Ethernet communications for PACSystems, please refer to the following manuals: PACSystems RX7i, RX3i and RSTi-EP TCP/IP Ethernet Communications User Manual, GFK-2224 PACSystems TCP/IP Ethernet Communications Station Manager User Manual, GFK-2225. 5.1.1 Embedded Ethernet Interface...
Chapter 5. Communications The following examples would be problematic: Problem example #1: Figure 45: CPE330 Overlapping Local IP Subnet Example The issue demonstrated in Figure 45 is that requests entering one CPE330 interface can be routed out the other interface since both CPE330 Ethernet ports have been configured to be on the same network (255.255.0.0) but are physically connected to separate networks.
Chapter 5. Communications Figure 46: Expected Response Path Figure 47: Actual Response Path PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD...
Chapter 5. Communications RX7i RX7i CPUs have an embedded Ethernet interface that provides TCP/IP communications with programming software and other control systems. These communications use the proprietary SRTP protocol and the standard Modbus/TCP protocol over a four-layer TCP/IP (Internet) stack. The Ethernet interface also supports Ethernet Global Data protocol using UDP (User Datagram Protocol).
Chapter 5. Communications 10Base-T/100Base-Tx Port Pin Assignments Pin assignments are the same for the RX3i and RX7i embedded Ethernet ports. Pin Number Signal Description Transmit Data + Transmit Data - Receive Data + No connection No connection Receive Data - No connection No connection Recovering a Lost IP Address...
RX7i CPU Features and Specifications), the RX7i and RX3i systems support rack-based Ethernet Interface modules. These modules are not interchangeable. For details about the capabilities, installation, and operation of these modules, refer to PACSystems RX7i & RX3i TCP/IP Ethernet Communications User Manual GFK-2224 and PACSystems TCP/IP Ethernet Communications Station Manager User Manual, GFK-2225.
Chapter 5. Communications Serial Communications RX3i CPUs, except CPE330, support one or more serial ports (see Section 2.2). RX7i CPUs support three serial ports (see Section 2.3). The independent on-board serial ports of the CPU are accessed via external connectors on the module. COM1 and COM2 provide serial interfaces to external devices.
Chapter 5. Communications Features Supported Serial Port 3 Serial Port 1 Serial Port 2 Feature (Station Mgr) (COM1) (COM2) RX7i only RTU Slave protocol SNP Slave Serial I/O – used with COMMREQs Firmware Upgrade PLC in (WinLoader utility) STOP/No IO mode Message Mode –used only with C blocks (C Runtime Library Functions: serial read, serial write, sscanf, sprintf)
Chapter 5. Communications 5.2.2 Configurable STOP Mode Protocols You can configure the protocol to be used in STOP Mode, based upon the configured serial port (RUN Mode) protocol. The Run/Stop protocol switching is independently configured for each serial port. The RUN Mode protocol setting determines which choices are available for STOP Mode. If a STOP Mode protocol is not selected, the default STOP Mode protocol is used.
Chapter 5. Communications 5.2.3 Serial Port Pin Assignments COM1 (RS-232, 9-pin Subminiature D Connector) This port has a 9-pin, female, D-sub connector with a standard pin out. This is a DCE (data communications equipment) port that allows a simple straight-through cable to connect with a standard AT-style RS-232 port.
Chapter 5. Communications COM1 (RS232, RJ45 Connector) The RJ45 Connector is provided for COM1 on CPE400 only. It has the following pinout. Pin No. Signal Name Description No Connection No Connection Transmit Data Receive Data Signal Ground No Connection No Connection No Connection Figure 48: COM1 Port CPE400 COM2 (RS-485, 15-pin Female D-sub Connector) –RX7i CPU/CRU Models...
Chapter 5. Communications COM2 (RS-485, 15-pin Female D-sub Connector) – All RX3i CPU/CRU Models & RX3i CPE310 This is a DCE port that allows a simple straight-through cable to connect with a standard AT-style RS-232 port. COM2 RS-485 Signals Pin No. Signal Name Description Shield Cable Shield Located at the bottom right of the connector as viewed from the front of the...
Chapter 5. Communications COM3 (RX7i only) COM3, the Station Manager serial port used to support the embedded Ethernet Interface, is RS-232 compatible. COM3 has a 9-pin, female, D-connector. This is a DCE port that allows a simple straight- through cable to connect with a standard AT-style RS-232 port. This port contains full use of the standard RS-232 signals for future use with point-to-point protocol (PPP).
Chapter 5. Communications 5.2.4 Serial Port Electrical Isolation Some serial communication ports are isolated, while others are not, as indicated in the following table: Family Model COM1 COM2 COM3 RX3i CPU310 Non-Isolated Non-Isolated CPU315 Non-Isolated Non-Isolated CPU320/CRU320 Non-Isolated Non-Isolated CPE302/CPE305 Non-Isolated CPE310 Non-Isolated...
Shielded cable optional (RX7i only) (RS-232) Note: For details on conformance to radiated emissions standards, refer to Appendix A in the following manuals: PACSystems RX7i Installation Manual, GFK-2223 PACSystems RX3i System Manual, GFK-2314 PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD...
5.3.1 Communications Coprocessor Module (CMM) PACSystems RX7i CPUs with versions 1.50 and higher support IC697CMM711 modules with firmware versions 4.20 and higher. You must ensure that you are using a valid version of the CMM firmware because the CPU cannot check the CMM’s firmware version. (The module’s firmware version can be found on a label attached to the EEPROM.)
If an application program running on the PCM accesses the VME bus, the VME addresses being used by that program must agree with the PACSystems RX7i VME address assignments. The PACSystems RX7i VME address assignments are described in the PACSystems RX7i User’s Guide to Integration of VME Modules, GFK-2235.
Chapter 5. Communications 5.3.3 DLAN/DLAN+ (Drives Local Area Network) Interface PACSystems RX7i CPUs with versions 1.50 and higher support IC697BEM763 modules with firmware versions 3.00 and higher. You must ensure that you are using a valid version of the PCM firmware because the CPU cannot check the DLAN’s firmware version.
Chapter 6 Serial I/O, SNP & RTU Protocols This chapter discusses the following topics related to communications on CPU serial ports COM1 and COM2: ▪ Configuring Serial Ports Using COMMREQ Function 65520 ▪ Serial I/O Protocol ▪ RTU Slave Protocol ▪...
CPU memory before it is executed. The COMMREQ should be executed by a contact of a one-shot coil to prevent sending the data multiple times. For details on the operands and command block format used by the COMMREQ function, refer to PACSystems RX7i and RX3i CPU Programmer’s Reference Manual, GFK-2950 Chapter 4.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.1.4 Invalid Port Configuration Combinations The Machine Edition programming software safeguards against the download of some hardware configurations that would prevent the programmer from communicating serially with the CPU. In a system that does not have an embedded Ethernet module, if a rack-based Ethernet is not present, a serial connection is required for programmer communications.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.1.5 COMMREQ Command Block Parameter Values The following table lists common parameter values that are used within the COMMREQ command blocks for configuring a serial port. All values are in decimal. Parameter Values Protocol Selector 1 = SNP...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.1.6 Example COMMREQ Command Blocks for Serial Port Setup function The following COMMREQ command blocks provide examples for configuring the various protocols. All values are in decimal unless followed by an H indicating hexadecimal. Note that an example is not provided for Message Mode, but it can be setup with a command block similar to the one for Serial I/O, with a value of 7 for the protocol selector.
Chapter 6. Serial I/O, SNP & RTU Protocols Example COMMREQ Data Block for Configuring RTU Protocol Values Meaning Address 13, or 17 Data Block Length Address + 1 0 = No Wait (WAIT mode not supported) WAIT/NOWAIT Flag Address + 2 0008 = %R, register memory Status Word Pointer Memory Type Zero-based number that gives the address of the...
Chapter 6. Serial I/O, SNP & RTU Protocols Example COMMREQ Data Block for Configuring Serial I/O Protocol Values Meaning Address Data Block Length Address + 1 0 = No Wait (WAIT mode not supported) WAIT/NOWAIT Flag Address + 2 0008 = %R, register memory Status Word Pointer Memory Type Zero-based number that gives the address of the Address + 3...
Chapter 6. Serial I/O, SNP & RTU Protocols Serial I/O Protocol Serial I/O protocol is a communication protocol that is driven entirely by the application program. Serial I/O protocol is active only when the CPU is in RUN Mode, since it is driven completely by COMMREQ functions in the application program.
Chapter 6. Serial I/O, SNP & RTU Protocols Major Error Code Description 13 (0Dh) Remote error — Error processing a remote command. The minor error code identifies the error. 2 (02h) Number of bytes requested to read is greater than input buffer size OR number bytes requested to write is zero or greater than 250 bytes.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.4 Serial I/O COMMREQ Commands The following COMMREQs are used to implement Serial I/O: ■ Local COMMREQs - do not receive or transmit data through the serial port. Initialize Port (4300) Set Up Input Buffer (4301) ...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.5 Overlapping COMMREQs Some Serial I/O COMMREQs must complete execution before another COMMREQ can be processed. Others can be left pending while others are executed. COMMREQS that Must Complete Execution ■ Autodial (4400) ■...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.6 Initialize Port Function (4300) This function causes a reset command to be sent to the specified port. It also cancels any COMMREQ currently in progress and flushes the internal input buffer. RTS and DTR are set to inactive. Example Command Block for the Initialize Port Function Value Value...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.7 Set Up Input Buffer Function (4301) This function is provided for compatibility with legacy Serial I/O applications. In PACSystems releases 5.70 and later, the internal input buffer is always set to 2097 bytes. In earlier PACSystems implementations, the internal input buffer is set to 2K bytes.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.8 Flush Input Buffer Function (4302) This operation empties the input buffer of any characters received through the serial port but not yet retrieved using a read command. All such characters are lost. Example Command Block for the Flush Input Buffer Function VALUE VALUE...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.9 Read Port Status Function (4303) This function returns the current status of the port. The following events can be detected: 1. A read request was initiated previously and the required number of characters has now been received or the specified time-out has elapsed.
Chapter 6. Serial I/O, SNP & RTU Protocols Port Status Word Meanings Name Definition Status Meaning Read Bytes or Read String invoked Read In progress Cleared Previous Read bytes or String has timed out, been canceled, or finished Read Bytes or Read String has successfully completed Read Success Cleared...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.10 Write Port Control Function (4304) This function controls output signals on the specified port: Example Command Block for the Write Port Control Function VALUE VALUE MEANING (decimal) (hexadecimal) Address 0002 0002 Data block length Address +1 0000 0000...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.11 Cancel COMMREQ Function (4399) This function cancels the current operations in progress. It can be used to cancel both read operations and write operations. If a read operation is in progress and there are unprocessed characters in the input buffer, those characters are left in the input buffer and available for future reads.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.12 Autodial Function (4400) This feature allows the CPU to automatically dial a modem and send a specified byte string. To implement this feature, the port must be configured for Serial I/O. After the autodial function is executed and the modem has established a connection, other serial I/O functions (Write bytes, Set Up Input Buffer, Flush Input buffer, Read port status, Write port control, Read bytes, Read String, and Cancel Operation) can be used.
Chapter 6. Serial I/O, SNP & RTU Protocols Sample Autodial Command Block This COMMREQ command block dials the number 234-5678 using a Hayes-compatible modem. Word Definition Values 0009h CUSTOM data block length (includes command string) 0000h NOWAIT mode 0008h Status word memory type (%R) 0000h Status word address minus 1 (Register 1) 0000h...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.13 Write Bytes Function (4401) This operation can be used to transmit one or more characters to the remote device through the specified serial port. The character(s) to be transmitted must be in a word reference memory. They should not be changed until the operation is complete.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.14 Read Bytes Function (4402) This function causes one or more characters to be read from the specified port. The characters are read from the internal input buffer and placed in the specified input data area. The function returns both the number of characters retrieved and the number of unprocessed characters still in the input buffer.
Chapter 6. Serial I/O, SNP & RTU Protocols Return Data Format for the Read Bytes Function The return data consists of the number of characters actually read, the number of characters still available in the input buffer after the read is complete (if any), and the actual input characters. Address Number of characters actually read Address + 1...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.2.15 Read String Function (4403) This function causes characters to be read from the specified port until a specified terminating character is received. The characters are read from the internal input buffer and placed in the specified input data area.
Chapter 6. Serial I/O, SNP & RTU Protocols Return Data Format for the Read String Function The return data consists of the number of characters actually read, the number of characters still available in the input buffer after the read is complete (if any), and the actual input characters: Address Number of characters actually read Address + 1 Number of characters still available in the input buffer, if any...
Chapter 6. Serial I/O, SNP & RTU Protocols RTU Slave Protocol RTU protocol is a query-response protocol used for communication between the RTU device and a host computer, which is capable of communicating using RTU protocol. The host computer is the master device and it transmits a query to a RTU slave, which responds to the master.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.3.1 Message Format The general formats for RTU message transfers are shown below: RTU Message Transfers Slave Turn-around Time Master Query Message Slave Response Query Transaction Master Broadcast Message Slave (No Response) Broadcast Transaction Figure 49: RTU Message Transactions The master device begins a data transfer by sending a query or broadcast request message.
Chapter 6. Serial I/O, SNP & RTU Protocols Message Types The RTU protocol has four message types: query, normal response, error response, and broadcast. Query The master sends a message addressed to a single slave. Normal Response After the slave performs the function requested by the query, it sends back a normal response for that function.
Chapter 6. Serial I/O, SNP & RTU Protocols Message Fields The message fields for a typical message are shown in the figure below, and are explained in the following sections. FRAME Station Address Function Code Information Error Check Station Address The Station Address is the address of the slave station selected for this data transfer.
Chapter 6. Serial I/O, SNP & RTU Protocols Information Fields All message fields, other than the Station Address field, Function Code field, and Error Check field are called, generically, information fields. Information fields contain additional information required to specify or respond to a requested function. Different types of messages have different types or numbers of information fields.
Chapter 6. Serial I/O, SNP & RTU Protocols Message Length Message length varies with the type of message and amount of data to be sent. Information for determining message length for individual messages is found in RTU Message Descriptions. Character Format A message is sent as a series of characters.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.3.2 Cyclic Redundancy Check (CRC) The CRC is one of the most effective systems for checking errors. The CRC consists of two check characters generated at the transmitter and added at the end of the transmitted data characters. Using the same method, the receiver generates its own CRC for the incoming data and compares it to the CRC sent by the transmitter to ensure proper transmission.
Chapter 6. Serial I/O, SNP & RTU Protocols Calculating the CRC-16 The pseudo code for calculation of the CRC-16 is given below. Preset byte count for data to be sent. Initialize the 16-bit remainder (CRC) register to all ones. XOR the first 8-bit data byte with the high order byte of the 16-bit CRC register. The result is the current CRC.
Chapter 6. Serial I/O, SNP & RTU Protocols Transmitter CRC-16 Algorithm Receiver CRC-16 Algorithm Flag Flag Initial Remainder 1111 1111 1111 1111 Rcvr CRC after data 1110 0010 0100 0001 XOR 1st data byte 0000 0000 0000 0001 XOR 1st byte Trns CRC 0000 0000 0100...
Chapter 6. Serial I/O, SNP & RTU Protocols Calculating the Length of Frame To generate the CRC-16 for any message, the message length must be known. The length for all types of messages can be determined from the table below. RTU Message Length Function Name...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.3.3 RTU Message Descriptions This section presents the format and fields for each RTU message. Message (01): Read Output Table Format: Starting Number of Error Address Func Points Point No. Check Query Error Address Data...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (04): Read Analog Inputs Format: Address Func Starting Number of Error Analog Input Analog Check Inputs Query Error Address Func Data Byte First Check Analog Count Input Normal Response Figure 55: RTU Read Analog Inputs Message Format Query: ▪...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (05): Force Single Output Format: Func Address Point Error Check Data Number Query Func Address Point Error Check Data Number Normal Response Figure 56: RTU Force Single Output Message Format Query: ▪...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (06): Preset Single Register Format: Address Func Register Error Check Data Number Query Func Address Register Error Check Data Number Normal Response Figure 57: RTU Preset Single Register Message Format Query: ▪...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (07): Read Exception Status Format: Func Address Error Check Query Func Error Check Address Data Normal Response Figure 58: RTU Read Exception Status Message Format Query: This query is a short form of request for the purpose of reading the first eight output points. ▪...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (08): Loopback/Maintenance (General) Format: Func Diagnostic Address Error Check Data c Code 0, 1, or 4 DATA 1 DATA 1 Query Func Diagnostic Address Error Check Data c Code 0, 1, or 4 DATA 1 DATA 1 Normal Response Figure 59: RTU Loopback/Maintenance Message Format...
Chapter 6. Serial I/O, SNP & RTU Protocols Response: ▪ See descriptions for individual Diagnostic Codes. Diagnostic Return Query Data Request (Loopback/Maintenance Code 00): ▪ An address of 0 is not allowed for the return query data request. ▪ The values of the two Data field bytes in the query are arbitrary. ▪...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (15): Force Multiple Outputs Format: Address Func Starting Number Error Check Byte Data Point Count Point No. of Points Query Func Number Starting Address Error Check Point of Points Point No. Normal Response Figure 60: RTU Force Multiple Outputs Message Format Query:...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (16): Preset Multiple Registers Format: Address Func Starting Number of Error Check Byte Data Point Count Registers Query Number of Func Starting Address Error Check Register No. Registers Normal Response Figure 61: RTU Preset Multiple Registers Message Format Query: ▪...
Chapter 6. Serial I/O, SNP & RTU Protocols Message (17): Report Device Type Format: Func 17 Address Error Check Query Address Func 17 Byte Device Slave Run Data Error Check Count Light Type 43 Normal Response Figure 62: RTU Report Device Type Message Format Query: The Report Device Type query is sent by the master to a slave in order to learn what type of programmable control or another computer it is.
Chapter 6. Serial I/O, SNP & RTU Protocols Message (22): Mask Write 4x Memory Modifies the contents of a specified 4x register using a combination of an AND mask, an OR mask, and the register's current contents. The function can be used to set or clear individual bits in the register. Broadcast is not supported.
Chapter 6. Serial I/O, SNP & RTU Protocols Message (23): Read Write 4x Memory Performs a combination of one read and one write operation in a single Modbus transaction. The function can write new contents to a group of 4x registers, and then return the contents of another group of 4x registers.
Chapter 6. Serial I/O, SNP & RTU Protocols Response: The normal response contains the data from the group of registers that were read. The Byte Count field specifies the quantity of bytes to follow in the Read Data field. Here is an example of a response to the query: Field Name Example (Hex)
Chapter 6. Serial I/O, SNP & RTU Protocols 6.3.4 RTU Scratch Pad The entire scratch pad is updated every time an external READ request is received by the PACSystems RTU slave. All scratch pad locations are read only. The scratch pad is a byte-oriented memory type. RTU Scratch Pad Memory Allocation Bits SP Address Field Identifier...
Chapter 6. Serial I/O, SNP & RTU Protocols 6.3.5 Communication Errors Serial link communication errors are divided into three groups: ▪ Invalid Query Message ▪ Serial Link Time Outs ▪ Invalid Transaction Invalid Query Message When the communications module receives a query addressed to itself, but cannot process the query, it sends one of the following error responses: Subcode Invalid Function Code...
Chapter 6. Serial I/O, SNP & RTU Protocols Invalid Address Error Response (2) An error response with a subcode of 2 is called an invalid address error response. This error response is sent in the following cases: 1. The Starting Point Number and Number of Points fields specify output points or input points that are not available in the attached CPU (returned for function codes 1, 2, 15).
Chapter 6. Serial I/O, SNP & RTU Protocols Serial Link Timeout The only cause for a RTU device to timeout is if an interruption to a data stream of 4 character times occurs while a message is being received. If this occurs the message is considered to have terminated and no response will be sent to the master.
Chapter 6. Serial I/O, SNP & RTU Protocols 6.3.6 RTU Slave/SNP Slave Operation with Programmer Attached A port that has been configured for RTU Slave protocol can switch to SNP protocol if an SNP master such as a programmer begins communicating to the port. The programmer must use the same serial communications parameters (baud rate, parity, stop bits, etc.) as the currently active RTU Slave protocol for it to be recognized.
Chapter 6. Serial I/O, SNP & RTU Protocols SNP Slave Protocol PACSystems CPUs can communicate with Machine Edition software through either COM1 or COM2 using SNP slave protocol. CPU COM1 is wired as an RS-232 Data Communications Equipment (DCE) port, and can be connected directly using straight-through cable to one of the serial ports of a PC running Machine Edition or other SNP master software.
Appendix A Performance Data This appendix contains instruction and overhead timing collected for each PACSystems CPU module. This timing information can be used to predict CPU sweep times. The information in this appendix is organized as follows: ▪ Boolean Execution Times ▪...
Appendix A. Performance Data A-1 Boolean Execution Times Boolean execution times for contacts and coils depend on several factors, including the CPU model, the type of reference address associated with the contact/coil, and whether the address is used directly or passed as a parameter.
Appendix A. Performance Data A-2 Instruction Timing A-2.1 Overview The tables in this section list the execution and incremental times in microseconds (µs) for each function supported by the PACSystems CPUs. Two execution times are shown for each instruction. Execution Time Description Enabled Time in µs required to execute the function or function block when power flows...
Appendix A. Performance Data A-2.2 PLC Version Information The instruction execution and incremental times were obtained by testing the following CPU versions: Model PLC Firmware Version All instructions RSTi-EP EPSCPE100 9.15 except as listed below RSTi-EP EPSCPE115 9.45 IC695CPE400 9.00 IC695CPE305/CPE310/CPE330 7.10 IC695CPE302...
Appendix A. Performance Data A-2.3 RX3i & RSTi-EP Instruction Times The following tables are intended to provide guidance for expected instruction execution times when using Ladder Diagram (LD) and C Language. For simplicity, the instructions are grouped as follows: • Boolean Operation: this includes coil and contact operation (LD only).
Appendix A. Performance Data RX7i Incremental Times An Increment time is shown for functions that can have variable length inputs. Incremental time is added to the base function time for each addition to the length of an input parameter. This time applies only to functions that can have varying input lengths (Search, Array Moves, etc.) Units: For table functions, increment is in units of length specified.
Appendix A. Performance Data A-3 Overhead Sweep Impact Times This section contains overhead timing information for the PACSystems CPUs. This information can be used in conjunction with the estimated logic execution time to predict sweep times for the CPUs. The information in this section is made up of a base sweep time plus sweep impact times for each of the CPU models.
Appendix A. Performance Data A-3.1 Base Sweep Times Base sweep time is the time for an empty _MAIN program block to execute, with no configuration stored and none of the windows active. The following table gives the base sweep times in microseconds (µs) for each CPU model.
Appendix A. Performance Data The following diagram shows the differences between the full sweep phases and the base sweep phases. Base Sweep vs. Full Sweep Phases Base Sweep Full Sweep <START OF SWEEP> <START OF SWEEP> Sweep Housekeeping Sweep Housekeeping ...
Appendix A. Performance Data A-3.2 What the Sweep Impact Tables Contain In some tables, functions are shown as asynchronously impacting the sweep. This means that there is not a set phase of the sweep in which the function takes place. For instance, the scanning of all I/O modules takes place during either the input or output scan phase of the CPU’s sweep.
Appendix A. Performance Data A-3.4 I/O Scan and I/O Fault Sweep Impact The I/O scan sweep impact has two parts, Local I/O and Genius I/O. The equation for computing I/O scan sweep impact is: I/O Scan Sweep Impact Local Scan Impact Genius I/O Scan Impact Sweep Impact of Local I/O Modules...
Appendix A. Performance Data RX7i Module Sweep Impact Times The following table provides sweep impact times for modules in the Main rack and in an expansion (Exp) rack. The base case provides the overhead a single module in the rack. The increment (Inc) refers to the overhead for each similar module that is added to the same rack.
Appendix A. Performance Data RX3i I/O Module Types Type Part Numbers Discrete Input, 16-point IC694MDL240, IC694MDL241, IC694MDL645, IC694MDL646 Discrete Input - Smart Digital Input, IC695MDL664 16-point Discrete Input, 32-point IC694MDL654, IC694MDL655, IC694MDL654 Discrete Output, 8-point IC694MDL330, IC694MDL732, IC694MDL930, IC694MDL940 Discrete Output, 16-point and IC694MDL340, IC694MDL341, IC694MDL740, IC694MDL741 12-point Discrete Output –...
Appendix A. Performance Data RX3i I/O Module Sweep Impact Times The following table provides sweep impact times for modules in the Main rack and in an expansion (Exp) rack. The base case provides the overhead for a single module in the rack. The increment (Inc) refers to the overhead for each similar module that is added to the same rack.
Appendix A. Performance Data Worksheet A: I/O Module Sweep Time The following form can be used for computing I/O module sweep impact. The calculation contains times for analog input expanders that are either grouped into the same scan segment as the preceding module or are grouped in a separate new scan segment.
Appendix A. Performance Data Sweep Impact of Genius I/O and GBCs For the sweep impact of Genius I/O and Genius Bus Controllers (GBC), there is a sweep impact for each GBC, a sweep impact for each scan segment, and a transfer time (per word) sweep impact for all I/O data. The GBC sweep impact has three parts: 1.
Appendix A. Performance Data Worksheet B: Genius I/O Sweep Time Use the following worksheet for predicting the sweep impact due to Genius I/O. The sweep impact times can be found in Sweep Impact Time of Genius I/O and GBCs. Open backplane communications window ______ = ______ ______...
Appendix A. Performance Data A-3.5 Ethernet Global Data Sweep Impact Note: Refer to Section, A-3.6 for information on standalone models supporting Embedded Ethernet interface. Depending on the relationship between the CPU sweep time and an Ethernet Global Data (EGD) exchange’s period, the exchange’s data may be transferred every sweep or periodically after some number of sweeps.
Appendix A. Performance Data Data Transfer Time Note: This is the time required to transfer the data between the CPU module and the rack-based Ethernet module. EGD data transfer times do not increase linearly in relation to data size. Please use the data values in the table below to estimate data transfer times. Note: CPE modules do not need to use this table with respect their embedded Ethernet port, as there is no transfer of data across the backplane related to EGD traffic.
Appendix A. Performance Data Embedded Rack-based Data Size (Bytes) Direction Ethernet Ethernet Module Interface (µS) (µS) CPE030 Consume / READ Consume / READ 25.8 18.7 Consume / READ 50.7 33.4 Consume / READ 60.1 40.4 Produce / WRITE Produce / WRITE 13.1 Produce / WRITE 18.2...
Appendix A. Performance Data A-3.6 EGD Sweep Impact for Embedded Ethernet Interface on RX3i & RSTi-EP CPE Models EGD Sweep Impact for RX3i CPE330 and CPE400 The CPE330 and CPE400 process Ethernet communications independently from logic and sweep execution. This architecture precludes the possibility of Ethernet communications causing the watchdog timer to time out.
Appendix A. Performance Data Example Calculation for EGD Utilization on RX3i CPE302/CPE305/CPE310 and RSTi-EP CPE100/CPE115 The watchdog time configured to 200ms for calculations in the table below: SN EGD Exchange Type of Exchange Period Total_EgdImpactPerWDT_ms[n] 1 EGD Exchange#1 Producer 1.600 2 EGD Exchange#2 Producer 1.600...
Appendix A. Performance Data Production Period Data size per Exchange Maximum Number of EGD [Consumption Timeout*] (Bytes) Exchanges ( Recommended) (ms) 1400 1400 1400 1400 1400 1400 1400 The following table shows the chart for setting up EGD exchanges on Embedded Ethernet for RSTi-EP CPE100/CPE115 with a no sweep load and no network traffic.
Appendix A. Performance Data Note: The Consumption Timeout is set at twice the Production Period on the other consuming RX3i CPE310 / RSTi-EP CPE100/CPE115 node. For example, for A, the Production Period for all the Producer exchanges is set to 500ms. This indicates that the Consumption Timeout for all the consumer exchanges on the consuming node is set to 1000ms (twice the production period).
Appendix A. Performance Data A-3.7 Sweep Impact of Intelligent Option Modules The tables in this section list the sweep impact times in microseconds (µs) for intelligent option modules. The fixed sweep impact is the sum of the polling sweep impact and the I/O scan impact. The opening of the Backplane Communications Window and the polling of each module have relatively small impacts compared to the sweep impact of CPU memory read or write requests.
Appendix A. Performance Data PROFINET Controller (PNC001) and PROFINET I/O Sweep Impact The PLC CPU sweep impact for a PROFINET IO network is a function of the number of PNCs, the number of PROFINET devices, and the number of each PROFINET device’s IO modules. The table below shows the measured sweep impact of the RX3i PROFINET Controller, supported VersaMax PROFINET devices, and I/O modules.
Appendix A. Performance Data DSM314 Sweep Impact Rx3i CPU310 Rack (µs) Rx3i NIU001+ Rack (µs) No. of Axes Configured Main Main 1535 2160 1830 2360 2018 2906 2304 3160 2500 6371 2840 3920 2990 4430 3350 4680 PACSystems* RX7i, RX3i and RSTi-EP CPU Reference Manual GFK-2222AD...
Appendix A. Performance Data A-3.8 I/O Interrupt Performance and Sweep Impact There are several important performance numbers for I/O interrupt blocks. The sweep impact of an I/O interrupt invoking an empty block measures the overall time of fielding the interrupt, starting up the block, exiting the block, and restarting the interrupted task.
Appendix A. Performance Data I/O Interrupt Block Performance and Sweep Impact Times CPE302 CPU310 CPU315/ CPE010 CPE020 CPE030 CPE040 Sweep Impact Item CPE305 (µs) CPU320 (µs) (µs) (µs) (µs) CPE310 (µs) (µs) I/O interrupt sweep impact 127.8 309.7 125.6 24.0 Minimum response time —...
Appendix A. Performance Data Worksheet D: Programmer, IOM, I/O Interrupt Sweep Time The following worksheet can be used to calculate the sweep impact times of programmer sweep impact, intelligent option modules, and I/O Interrupts. For time data, refer to the following tables: Programmer Sweep Impact Times RX7i Module Sweep Impact Times or RX3i I/O Module Sweep Impact Times Sweep Impact Time of Genius I/O and GBCs...
Appendix A. Performance Data A-3.9 Timed Interrupt Performance The sweep impact of a timed interrupt invoking an empty program block or timed program measures the overall time of fielding the interrupt, starting up the program or block, exiting the program or block, and restarting the interrupted task.
Appendix A. Performance Data A-3.10 Example of Predicted Sweep Time Calculation The sweep time estimate in this example does not include a time for logic execution. The calculated sweep is for normal sweep time with point faults disabled, and the programmer is not attached. The times used in the calculation are extracted from the following tables: Base Sweep Times RX7i Module Sweep Impact Times or RX3i I/O Module Sweep Impact Times...
Appendix B User Memory Allocation User Memory Size is the number of bytes of memory available to the user for PLC applications. Model User Memory Size (MB) IC695CPE302 IC695CPE305 IC695CPU310, IC695CPE310, IC698CPE010, IC698CPE020, IC698CRE020 10MB IC695CPU315 20MB IC695CPE400, IC695CPE330, IC695CPU320, IC695CRU320 64MB IC698CPE030, IC698CRE030 64MB...
Appendix B. User Memory Allocation B-1 Items that Count Against User Memory The following items count against the CPU memory and can be used to estimate the minimum amount of memory required for an application. Additional space may be required for items such as Advanced User Parameters, zipped source files, user heap, and published symbols.
Appendix B. User Memory Allocation B-2 User Program Memory Usage Space required for user logic includes the following items. B-2.1 %L and %P Program Memory %L and %P are charged against your user space and sized depending on their use in your applications. The maximum size of %L or %P is 8192 words per block.