Overview Of The Spi Bus Signal Analysis Function - YOKOGAWA DL7480 User Manual

Chapter 3 SPI Bus Signal Analysis Function
3.1 Overview of the SPI Bus Signal Analysis
Function
About the SPI Bus Signal Analysis Function
Trigger Function <See page 3-5 for the operating procedure>
Byte level
IM 701450-51E
The SPI (Serial Peripheral Interface) Bus is a synchronized serial bus that is widely used
for inter-IC communications and data communications.
By using this function, you will be able to analyze data while displaying the SPI Bus
signal waveform.
The SPI Bus signal analysis function consists of the following three main functions.
Acquires SPI Bus signals by comparing the specified conditions with the master output
slave input signal (MOSI)* or master input slave output signal (MISO)* at the byte level
(8 bits). MOSI or MISO data is divided into 8 bits from the valid edge of the clock signal
(SCK)* immediately after the assertion of the slave select signal (SS).* If the number of
bits is not an integer multiple of 8, data is compared every 8 bits from the first edge, but
the last data that is less than 8 bits is not compared.
* On the DL7440/DL7480, the SCK (clock signal), MOSI (master output slave input signal),
MISO (master input slave output signal), and SS (slave select signal) are applied to CH1,
CH2, CH3, and CH4, respectively.
SS
SCK
1 2 4 5
3
MOSI
0 0 0 0 1
MISO 1 1 0 0 0
1
To activate triggers on the DL7440/DL7480, you will set pattern A/B and/or byte count.
Triggers can be activated in various ways such as when the MOSI data pattern matches
pattern A; the specified byte count after the MOSI data pattern matches pattern A; or
when the MISO data pattern matches pattern B after the specified byte count elapses
after the MOSI data pattern matches pattern A.
To activate a trigger the specified byte count after MOSI matches Pattern A
(Number of bytes of Pattern A: 4, byte count: 3)
SS
Byte level of MOSI 1 2
Compare with
Pattern A
On the DL7480, triggers can also be activated by combining the trigger conditions of the
SPI Bus signal and the parallel pattern of CH5 to CH8.
8n+1
6 7 8 9 10
8n
0 0 0 0 0 0 0 1
1 0 0 0 1 0 0 0
2 n
1st byte nth byte
...
3 4 5 6 7 8
Byte
Trigger activated here
count
8n+3
8n+2
8n+4
0 0 0
1 1 1
n+1
n+1th byte is less than
8 bits and is not applicable
for triggering.
3-1
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