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Local Memory
Local memory is used for data and program storage and is implemented using block RAM.
The size of the local memory is parameterized and can be between 4kB and 64kB. The local
memory is connected to MicroBlaze through the Local Memory Bus, LMB, and the LMB
BRAM Interface Controllers. Detailed information on LMB can be found in the Local Memory
Bus (LMB) V10 data sheet
Controller can be found in the LMB BRAM Interface Controller data sheet
The LMB Bus and the LMB BRAM Interface Controller parameters are fixed except for the
memory size. The value of the parameters can be found in
and
Table
4-7.
Debug
The MicroBlaze Debug Module, MDM, connects MicroBlaze debug logic to the XMD low
level debugger. XMD can be used for downloading software, to set break points, view
register and memory contents. Detailed information about MDM can be found in the
MicroBlaze Debug Module (MDM) data sheet
The MDM parameters, except the JTAG user-defined register, are fixed and their values can
be found in
Table
When more than one MicroBlaze MCS instance with debug enabled is included in the same
design, a unique JTAG register must be used for each instance. When a single instance is
used, the default value USER2 should be kept unchanged.
I/O Module
The I/O Module is a light-weight implementation of a set of standard I/O functions
commonly used in a MicroBlaze processor sub-system. Detailed information about the I/O
Module can be found in the I/O Module product guide
The I/O Module registers are mapped at address 0x4000000, and the I/O Bus is mapped at
address 0xC0000000-0xFFFFFFFF in the MicroBlaze memory space. The fixed I/O Module
parameter values can be found in
Licensing and Ordering Information
This Xilinx LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado™
Design Suite and ISE® Design Suite tools under the terms of the
Information about this and other Xilinx LogiCORE IP modules is available at the
Intellectual Property
LogiCORE IP modules and tools, contact your
MicroBlaze Micro Controller System v1.3
PG048 December 18, 2012
[Ref 1]
and detailed information on the LMB BRAM Interface
4-8.
Table
4-3.
page. For information about pricing and availability of other Xilinx
www.xilinx.com
Table
4-4,
[Ref
3].
[Ref
4].
Xilinx End User
local Xilinx sales
representative.
Chapter 1: Overview
[Ref
2].
Table
4-5,
Table 4-6
License.
Xilinx
6
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