Simulation Debug - Xilinx LogiCORE MicroBlaze Product Manual

Step:
Corrective actions: Run Data2MEM manually to create simulation files, or invoke the
Step:
Tool:
Problem:
Possible causes:
Corrective actions: • Run data2mem manually to configure the bitstream with software, or invoke the

Simulation Debug

The simulation debug flow for ModelSim is described below. A similar approach can be
used with other simulators.
• Check for the latest supported versions of ModelSim in the
Notes Guide. Is this version being used? If not, update to this version.
• If using Verilog, do you have a mixed mode simulation license? If not, obtain a
mixed-mode license.
• Ensure that the proper libraries are compiled and mapped. In ISE Project Navigator this
is done by clicking on Simulation view, selecting the device in Behavioral Hierarchy
and then selecting Run in the context menu for Compile HDL Simulation Libraries in
the Design tab below. In PlanAhead and Vivado Design Suite Flow
Settings can be used to define the libraries.
• Have you associated the intended software program for the MicroBlaze processor with
the simulation? Use the microblaze_mcs_data2mem Tcl procedure to do this in ISE
Project Navigator or PlanAhead. The equivalent command in Vivado Design Suite is
>
Tools Associate ELF Files.
MicroBlaze Micro Controller System v1.3
PG048 December 18, 2012
Simulate Software
microblaze_mcs_data2mem command with the appropriate ELF files as
arguments.
Download and Run Software
Impact
No output or mangled output on the UART console.
• The bitstream has not been configured with software.
• Frequency defined in the MicroBlaze MCS settings does not match actual
frequency of the connected clock input.
• Baud rate and/or other UART setting, defined in the MicroBlaze MCS settings, do
not match the terminal program settings.
microblaze_mcs_data2mem command with the appropriate ELF files as
arguments.
• Correct the frequency in the MicroBlaze MCS configuration dialog.
• Change the terminal program settings to match the MicroBlaze MCS
configuration.
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Appendix B: Debugging
Xilinx Design Tools: Release
>
Simulation
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