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In Vivado or PlanAhead this file is typically called project-name.runs/
impl_1/toplevel.bit.
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In Project Navigator this file is typically called toplevel.bit.
Click the second Browse button, and navigate to the BMM file updated with block
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RAM placement.
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In Vivado this file is typically called project-name.runs/impl_1/
toplevel_bd.bmm.
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In PlanAhead with one MicroBlaze MCS component, this file is typically called
project-name.srcs/sources_1/ip/component-name/
component_name_bd.bmm. With more than one MicroBlaze MCS component,
the merged BMM file updated with block RAM placement must be selected
instead.
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In Project Navigator with one MicroBlaze MCS component, this file is typically
called ipcore_dir/component_name_bd.bmm. With more than one
MicroBlaze MCS component, the merged BMM file updated with block RAM
placement must be selected instead.
Click Program to perform the import and program the FPGA.
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For additional information, see the Xilinx SDK Help
MicroBlaze Micro Controller System v1.3
PG048 December 18, 2012
Chapter 4: Customizing and Generating the Core
[Ref
6].
www.xilinx.com
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