Head Control Lsi (Mbcg46183-520Pf) - Fujitsu DL7600 Maintenance Manual

5.3.3 Head Control LSI (LFE2-12E-5FN484C)
Figure 5.3.11 and 5.3.12 is a head/motor control FPGA block diagram.
A1～A7
D00～D15
HDTIM
*APTCMC
*HCPPMC
*RPMC
*RPJSC
*FPJSC
*RTRPESC
*FTRPESC
*TOFRSC
*RPS
*APTCHPS
RTRPES
FTRPES
*HCPPPS
FCSFPES
RCSFPES
*LRES
SPTIM
MLFTIM
HDALM1～HDALM12
SPALMS
SPALML
MLFALMS
MLFALML
POWST1
Figure 5.3.11 Head/motor control FPGA block diagram
Address
decoder
Print head controller
General-purpose
Input port
Motor control
Interrupt control
Alarm detection
control
163
FPD1～FPD24
FFLYBK1～FFLYBK24
SPM0～SPM3
SPI0～SPI2
MLFM0～MLFM3
MLFI0～MLFI1
APTCM0～APTCM3
HCPPM0～HCPPM3
RPM0～RPM3
MT0I
*POWST
SG1