Fujitsu DL7600 Maintenance Manual page 171

[Error detection circuit]
① Over current detection
If the space motor, line feed motor, or tractor motor current exceeds the respective absolute rated value, an over
current detection signal is sent to the FPGA.
After a given period of the receipt of the detection signal, the FPGA controls the POWST signal to turn off +40 V.
It also notifies the MPU of the occurrence of a driver error.
[Open/close, APTC, and CSF motor control and drive circuits]
The phase data and switchover timing for the open/close, APTC, and CSF motors are controlled by FPGA motor control,
but current control is not performed.
[CSF short-circuit protection circuit]
If abnormal current flows to +40V for some reason, the fuse is blown to prevent +40 V from being supplied from
the main board (HGC07**).
FPGA
FPGA
FE2-12E-5FN484C FE2-12E-5FN484C
Figure 5.3.19 Open/close, APTC and CSF motor drive circuit block diagram
APTC motor APTC motor
APTCM0-3
drive circuit drive circuit
Open/close
motor rive
HCPPM0-3
circuit
Front CSF
drive
FCSFM0-3
circuit
Rear CSF
drive
RCSFM0-3
circuit
171
+40V
APTC motor
M
Open/close motor
M
Front CSF motor
M
Rear CSF motor
M