Support Of Multiple Cpu System Or Redundant System - Mitsubishi Electric QJ71C24N User Manual

Q corresponding serial communication module
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5 DATA COMMUNICATION USING THE MELSEC COMMUNICATION
PROTOCOL

5.1.4 Support of multiple CPU system or redundant system

5 - 3
(2) System settings using GX Configurator-SC
When it is necessary to change the default values registered in the Q series C24,
perform the settings as indicated in Chapter 9 and register these to the flash
ROM in the Q series C24.
• MC protocol system setting
• Transmission control and others system setting
POINT
To write from the external device to the intelligent function module installed in the
MELSECNET/H remote I/O station during communication using the MC protocol,
check "Enable Write at RUN time" on GX Developer.
When the external device accesses a QCPU in a multiple CPU system or redundant
system, it is possible to selectively access either a control or non-control CPU in the
multiple CPU system or a control or standby system CPU or System A or System B
CPU in the redundant system by specifying the target QCPU in "Requested module
I/O No." of the QnA compatible 4C frame for the MC protocol.
Refer to the Reference Manual for details.
Refer to Chapter 2 of this manual for the system configuration.
(Example) When multiple CPU No.1 is specified
E
N
Q
H
L
H
L
H
L
H
L
H
F
8
0
5
0
7
0
7
0
3
E
05
46
38
30
35
30
37
30
33
30
33
45
30
H
H
H
H
H
H
H
H
H
H
H
H
(Command massage of the QnA compatible 4C frame format 1)
REMARKS
• When using the Q series C24 in a multiple CPU system, it is necessary to specify
the QCPU that controls the Q series C24 (hereinafter referred to as the control
CPU) using GX Developer.
• It is also possible to mount a Q series C24 of function version A in a multiple CPU
system. In this case, it is only possible to access the control CPU (CPU No.1).
• It is only possible to access the control CPU if data is communicated by means of
frames other than the QnA compatible 4C frame.
• When the Q series C24 is mounted on the extension base unit of the redundant
system, the access target (control system CPU or standby system CPU and
system A CPU or system B CPU) that can be specified varies depending on each
command.
For details, refer to QnPRHCPU User's Manual (Redundant System).
L
H
L
H
L
H
L
H
L
0
0
0
0
0
0
4
0
1
0
0
0
1
30
30
30
30
30
34
30
31
30
30
30
31
H
H
H
H
H
H
H
H
H
H
H
H
MELSEC-Q
L
L
H
H
0
0
0
0
0
0
5
X
0
0
4
58
2A
30
30
30
30
34
30
30
30
30
35
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
3
6
33
36
H
H
5 - 3

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