CDM-550T Satellite Modem
7.1
Introduction ................................................................................................................................................7-1
7.2
Viterbi..........................................................................................................................................................7-1
7.3
Sequential ....................................................................................................................................................7-2
7.4
7.5
Turbo Product Codec (Option) .................................................................................................................7-4
7.1.1
End-to-End Processing Delay ..............................................................................................................7-6
7.6
Uncoded Operation (No FEC) ...................................................................................................................7-7
9.1
Introduction ................................................................................................................................................9-1
9.2
ASYNC EIA-232 Specifications.................................................................................................................9-1
9.3
Setup ............................................................................................................................................................9-2
9.4
Other Considerations .................................................................................................................................9-2
9.4.1
Baud Rate Accuracy ............................................................................................................................9-2
9.4.2
CHAPTER 10. CLOCKING....................................................................................... 10-1
10.1
Transmit Clocking ...............................................................................................................................10-1
10.1.1
Internal Clock ................................................................................................................................10-1
10.1.2
External Clock...............................................................................................................................10-1
10.1.3
Loop-Timed, RX=TX....................................................................................................................10-2
10.1.4
10.2
Receive Clocking ..................................................................................................................................10-2
10.2.1
Buffer Disabled .............................................................................................................................10-2
10.2.2
Buffer Enabled, RX=TX ...............................................................................................................10-2
10.2.3
10.3
X.21 Notes .............................................................................................................................................10-3
10.4
11.1
Theory Of Operation ...........................................................................................................................11-1
11.2
M&C Connection .................................................................................................................................11-2
11.3
Setup Summary ....................................................................................................................................11-3
Rev.1.3
Preface
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