Lvds Header Interface - Xilinx Virtex-4 FX FPGA User Manual

Detailed Description
Table 17: XGI Header (J14) (Continued)

12. LVDS Header Interface

The LVDS header interface allows the user to experiment with the LVDS I/O pairs as
shown in
purpose designated by the user.
Table 18: LVDS Header (J139)
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22
Pin Number ML421
36 J21
38 G21
40 F22
42 H24
44 G24
46 J23
48 K23
50 L24
52 M24
54 N24
56 N23
58 M22
60 N22
62 K20
64 L19
Table 18, page 22
Pin Number ML421
2
4
6
8
10
12
14
16
18
20
22
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ML423
F24
D25
C25
E27
D27
G25
F25
K26
J26
K24
L24
P24
N24
J22
K22
and Table 19, page 24. These I/O pins can also be used for any
ML423
D16
D15
C13
C12
D12
D11
C9
C8
D6
C5
G10
ML424
L29
J30
H30
E31
D31
D29
C29
G31
F31
G33
G32
C33
C32
D27
E27
ML424
D14
C14
K13
J12
D11
E11
E9
F9
C5
D5
C10
ML42x User Guide
UG087 (v1.3) May 30, 2008
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