Xilinx Virtex-4 FX FPGA User Manual page 23

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Table 18: LVDS Header (J139) (Continued)
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ML42x User Guide
UG087 (v1.3) May 30, 2008
Pin Number ML421
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
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ML423 ML424
H10 D10
G7 E8
H7 F8
M12 E3
M11 F3
AB11 AH14
AA11 AH13
AD12 AT15
AE12 AU15
AG13 AL13
AH13 AM13
AL8 AN8
AK8 AN7
AL10 AU10
AM10 AT10
AJ12 AP11
AK12 AR11
AK13 AK11
AL13 AJ11
AD14 AP16
AC13 AR16
Detailed Description
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