Revision History - Xilinx Virtex-4 FX FPGA User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
06/28/05 1.0
09/28/05 1.0.1
11/06/06 1.1
03/02/07 1.2
02/06/08 1.2.1
05/30/08 1.3
www.BDTIC.com/XILINX
ML42x User Guide
Initial Xilinx release.
In "Package Contents" section, added SMA wrench and deleted NQSL board.
Minor text edits for clarity.
Added "22. System ACE MPU Port"
Added "Additional Documentation"section. Updated
Added "Additional Information"
Updated Legal disclaimer. Updated the link to the product page in
Information."
Added the ML421 reference designators in
designators in Table 3, page
ML421 and ML423 in Table 3, page
Corrected pins 29, 31, 33, and 35 for ML424 in
ML421, ML423, and ML424 in
and 32 for ML424 in Table 18, page
Table 21, page 25. Corrected MPA00 and MPA04 for ML421, and MPA06 for ML423 in
Table 23, page 30.
www.xilinx.com
R
Revision
section. Miscellaneous typographical edits.
section.
Table 2, page
14. Corrected VTT RX LEFT and VTT RX RIGHT for the
14. Corrected labels for ML423 in
Table 14, page
Table 16, page 21. Corrected pin 62 for ML423 and pins 30
22. Corrected labels J115 through J118 for ML423 in
"Package Contents"section.
"Additional
13. Added the ML424 reference
Table 8, page
19. Corrected VCC for
UG087 (v1.3) May 30, 2008
16.