Xilinx Virtex-4 FX FPGA User Manual page 20

Detailed Description
Table 14: XGI Header (J13) (Continued)
The pin order in
not reflect the physical connection to this connector.
Table 15: XGI Header (J11)
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20
Pin Number ML421
57 AD16
59 AC16
61 AB15
63 AA15
Table 15 is arranged from top to bottom as viewed on the board. It does
Pin Number ML421
1 IIC
2 IIC
3 U24
4 T24
5 Y16
6 Y15
7 W24
8 V24
9 AF14
10 AF13
11 AD15
12 AD14
13 AD13
14 AC14
15 AC13
16 AC12
17 AB12
18 AA12
19 TDO
20 X TDO
21 TCK
22 TMS
23 NC
24 VCC3
25 VCC3
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ML423 ML424
AM22 AR26
AM21 AP26
AL19 AT24
AL18 AR24
ML423 ML424
IIC IIC
IIC IIC
AG18 AP35
AF18 AP34
AG16 AU26
AG17 AT26
AF19 AT35
AE17 AU35
AF21 AN20
AE21 AP20
AE16 AM22
AF16 AN22
AK29 AL19
AJ29 AL21
AK21 AK19
AL21 AJ19
AL29 AM21
AM30 AM20
TDO TDO
X TDO X TDO
TCK TCK
TMS TMS
NC NC
VCC3 VCC3
VCC3 VCC3
R
ML42x User Guide
UG087 (v1.3) May 30, 2008