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TMS320C6745, TMS320C6747
SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014
6.25 USB1 Host Controller Registers (USB1.1 OHCI)
All the device USB interfaces are compliant with Universal Serial Bus Specification, Revision 1.1.
Table 6-94
is the list of USB Host Controller registers.
BYTE ADDRESS
0x01E2 5000
0x01E2 5004
0x01E2 5008
0x01E2 500C
0x01E2 5010
0x01E2 5014
0x01E2 5018
0x01E2 501C
0x01E2 5020
0x01E2 5024
0x01E2 5028
0x01E2 502C
0x01E2 5030
0x01E2 5034
0x01E2 5038
0x01E2 503C
0x01E2 5040
0x01E2 5044
0x01E2 5048
0x01E2 504C
0x01E2 5050
0x01E2 5054
0x01E2 5058
(1) Restrictions apply to the physical addresses used in these registers.
(2) Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP).
(3) Although the controller implements two ports, the second port cannot be used.
Table 6-95. Switching Characteristics Over Recommended Operating Conditions for USB1
No.
U1
t
Rise time, USB1_DP and USB1_DM signals
r
U2
t
Fall time, USB1_DP and USB1_DM signals
f
U3
t
Rise/Fall time matching
RFM
U4
V
Output signal cross-over voltage
CRS
U5
t
Differential propagation jitter
j
U6
f
Operating frequency
op
(1) Low Speed: C
= 200 pF. High Speed: C
L
(2) t
=( t
/t
) x 100
RFM
r
f
(3) t
= t
- t
jr
px(1)
px(0)
(4) f
= 1/t
op
per
6.25.1 USB1 Unused Signal Configuration
If USB1 is unused, then the USB1 signals should be configured as shown in
184
Peripheral Information and Electrical Specifications
Table 6-94. USB1 Host Controller Registers
ACRONYM
HCREVISION
HCCONTROL
HCCOMMANDSTATUS
HCINTERRUPTSTATUS
HCINTERRUPTENABLE
HCINTERRUPTDISABLE
HCHCCA
HCPERIODCURRENTED
HCCONTROLHEADED
HCCONTROLCURRENTED
HCBULKHEADED
HCBULKCURRENTED
HCDONEHEAD
HCFMINTERVAL
HCFMREMAINING
HCFMNUMBER
HCPERIODICSTART
HCLSTHRESHOLD
HCRHDESCRIPTORA
HCRHDESCRIPTORB
HCRHSTATUS
HCRHPORTSTATUS1
HCRHPORTSTATUS2
PARAMETER
(2)
(1)
(3)
(4)
= 50pF
L
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REGISTER DESCRIPTION
OHCI Revision Number Register
HC Operating Mode Register
HC Command and Status Register
HC Interrupt and Status Register
HC Interrupt Enable Register
HC Interrupt Disable Register
HC HCAA Address Register
HC Current Periodic Register
HC Head Control Register
HC Current Control Register
(1)
HC Head Bulk Register
HC Current Bulk Register
(1)
HC Head Done Register
HC Frame Interval Register
HC Frame Remaining Register
HC Frame Number Register
HC Periodic Start Register
HC Low-Speed Threshold Register
HC Root Hub A Register
HC Root Hub B Register
HC Root Hub Status Register
HC Port 1 Status and Control Register
HC Port 2 Status and Control Register
LOW SPEED
MIN
(1)
(1)
75
(1)
(1)
75
(2)
80
(1)
1.3
(3)
-25
Copyright © 2008–2014, Texas Instruments Incorporated
TMS320C6745 TMS320C6747
(1)
(1)
(1)
(1)
(1)
(2)
(3)
FULL SPEED
MAX
MIN
MAX
(1)
(1)
(1)
300
4
20
(1)
(1)
(1)
300
4
20
(2)
(2)
(2)
120
90
110
(1)
(1)
(1)
2
1.3
2
(3)
(3)
(3)
25
-2
2
1.5
12
Section
3.6.23.
www.ti.com
UNIT
ns
ns
%
V
ns
MHz
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