National Instruments 653X User Manual page 79

High-speed digital i/o devices for pci, pxi, compactpci, at, eisa, and pcmcia bus systems
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Chapter 3
Timing Diagrams
ACK
REQ
Output Data Valid
(REQ-edge
latching)
Output Data Valid
(REQ-edge
latching disabled)
Parameter
Input Parameters
t
REQ pulse width
rr*
t
REQ inactive duration
r*r
t
ACK inactive to next REQ inactive
a*r*
Output Parameters
t
ACK pulse width
aa*
t
REQ inactive to new output data
r*do(1)
(with REQ-edge latching)
t
REQ inactive to new output data
r*do(2)
(with REQ-edge latching disabled)
t
Output data valid to ACK
doa
(with REQ-edge latching disabled)
1
t
(min) = 225 + programmable delay
aa*
2
t
(max) = 275 + programmable delay
aa*
When REQ-edge latching is disabled (default), output data valid will be held
Note
t
ns after the trailing edge of REQ occurs. With REQ-edge latching enabled, output
r*do(1)
data will be held at most t
653X User Manual
t
aa*
t
r*r
t
doa
Description
Figure 3-25. Trailing Edge Output Timing Diagram
ns after the trailing edge of REQ occurs.
r*do(1)
3-28
t
a*r*
t
rr*
t
r*do(1)
t
r*do(2)
ACK and REQ are shown as active high
Minimum
75
75
0
1
225
0
0
25
Maximum
2
275
50
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