National Instruments 653X User Manual page 54

during, or after the REQ edge. If STARTRIG is asserted too close to the REQ edge, it may
not be recognized until the next REQ edge. To avoid this uncertainty, you can observe an
optional setup time of 15 ns, in other words, assert STARTRIG at least 15 ns before the
start of the REQ pulse.
REQ
Data Valid
(Output Mode)
Data Valid
(Input Mode)
Parameter
t
c
t
hw
t
p
t
su
t
h
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The STARTRIG signal is synchronized to the REQ edge using a flip-flop.
Because of this synchronization flip-flop, there is a one REQ-pulse delay
after STARTRIG before the data capture begins. There is a possibility of a
two-cycle delay if you do not observe the optional setup time mentioned in
the previous note.
50 ns Min
t
hw
20 ns Min
t
su
10 ns
Min
Cycle time
Width of low pulse
Propagation time to valid output data
Setup time
Hold time
Figure 3-2. External Request Timing Diagram
t
c
t
w
20 ns Min
t
p
30 ns Max
t
h
20 ns
Min
Description
3-3
Chapter 3 Timing Diagrams
653X User Manual