National Instruments 653X User Manual page 61

Chapter 3 Timing Diagrams
PCLK
t
ACK
REQ
Data In Valid
Parameter
Input Parameters
t
PCLK cycle time
pc
t
PCLK high pulse duration
pw
t
PCLK low pulse duration
pl
Setup time from REQ valid to PCLK falling
t
rs
edge
t
Hold time from PCLK to REQ invalid
rh
t
Setup time from input data valid to PCLK
dis
falling edge
t
Hold time from PCLK to input data valid
dih
Output Parameters
t
PCLK to ACK valid
pa
t
Hold time from PCLK to ACK invalid
ah
All timing values are in nanoseconds.
653X User Manual
t
pw
pa
t
rs
t
dis
Description
Figure 3-7. Burst Input Timing Diagram (PCLK Reversed)
t
pc
t
pl
3-10
t
ah
t
rh
t
dih
Minimum Maximum
50
20
20
1
0
0
0
—
3
—
—
—
—
—
—
—
22
—
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