Chapter 3
Timing Diagrams
ACK
REQ
Input Data Valid
(REQ-edge
latching)
Input Data Valid
(REQ-edge
latching disabled)
Parameter
Input Parameters
t
REQ pulse width
rr*
t
REQ inactive duration
r*r
t
ACK to next REQ
ar
t
Input data setup to REQ active
dir(1)
(with REQ-edge latching)
t
Input data hold from REQ active
rdi
(with REQ-edge latching)
t
Input data setup to REQ
dir(2)
(with REQ-edge latching disabled)
t
Input data hold from ACK
adi
(with REQ-edge latching disabled)
Output Parameters
t
ACK pulse width
aa*
t
REQ to ACK inactive
ra*
All timing values are in nanoseconds.
653X User Manual
t
aa*
t
ra*
t
ar
t
r*r
t
t
dir(1)
rdi
t
dir(2)
Description
Figure 3-16. Level ACK Input Timing Diagram
3-20
t
rr*
ACK and REQ are shown as active high
Minimum
75
75
0
0
10
0
0
225
100
t
adi
Maximum
—
—
—
—
—
—
—
—
200
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