National Instruments 653X User Manual page 59

Chapter 3 Timing Diagrams
PCLK
t
ACK
REQ
Data In Valid
Parameter
Input Parameters
t Setup time from REQ valid to PCLK
rs
t
Hold time from PCLK to REQ invalid
rh
t
Setup time from input data valid to PCLK
dis
t
Hold time from PCLK to input data invalid
dih
Output Parameters
t
PCLK cycle time
pc
t
PCLK high pulse duration
pw
t
PCLK to ACK valid
pa
t
Hold time from PCLK to ACK invalid
ah
1
t = programmable delay from 100 to 700 ns, or 50 ns if programmable delay is 0. Timebase stability for the onboard
pc
20 MHz clock source is 100 ppm.
All timing values are in nanoseconds.
653X User Manual
t
pw
pa
Description
Figure 3-5. Burst Input Timing Diagram (Default)
t
pc
t
rs
t
dis
3-8
t
ah
t
rh
t
dih
Minimum Maximum
12
0
4
6
50 700
t /2 – 5 t
pc pc
—
3
—
—
—
—
1
/2 + 5
18
—
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