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Chapter 3
Timing Diagrams
dtp will remove bar
REQ
if Active High
REQ
if Active Low
Data Valid
(Output Mode)
Data Valid
(Input Mode)
Parameter
t
*
c
t
*
w
t
p
t
su
t
h
* The 6534 devices will transfer data at 20 MHz when the cycle time (t
pulse (t
) is 20–30 ns.
w
External REQ Signal Source
For data transfers that use a hardware start trigger, there is no mandatory setup (t
Note
or hold time (t
653X User Manual
Programmable = Interval x Timebase
t
c
Programmable = One Timebase
t
su
30 ns
Min
Cycle time
Width of pulse
Propagation time to valid output data
Setup time
Hold time
Figure 3-1. Internal Request Timing Diagram
Use an external request when you want to time data transfers using an
external signal on the REQ pin of the I/O connector. You can select the
polarity of the REQ signal. If active high (default), the 653X device will
latch the data on the I/O pins on the rising edge of the REQ signal. If active
low, the 653X device will latch the data on the I/O pins on the falling edge
of the REQ signal. The low time and high time of the REQ signal must each
be >20 ns. The minimum duration for a period of the REQ signal is 50 ns.
) for the STARTRIG (ACK) signal. It can be asserted at any point before,
h
t
w
t
p
30 ns
Max
t
h
0 ns
Min
Description
) for REQ pulse is 50 ns and width of the REQ
c
3-2
)
su
ni.com
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