Introduction; Features; Table 1-1 Cpci-6115 Features - Motorola CPCI-6115 Installation And Use Manual

Introduction

1.1

Features

The following table summarizes the features of the CPCI-6115 Single Board Computer (SBC).
The CPCI-6115 was formerly offered as the MCPN905 SBC.

Table 1-1 CPCI-6115 Features

Feature
Processor
L3 Cache
Flash
SDRAM
Memory Controllers
PCI Host Bridges
Interrupt Controller
PCI Interfaces
Ethernet Interface
SEEPROM
CompactPCI Interface
Form Factor
RTC/NVRAM
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Description
Single MPC7457 Processor
Core Frequency to 1.0 GHz
Bus Clock Frequency of 133 MHz
Integrated L1 and L2 cache
Address and data bus parity
1 MB or 2 MB DDR back side L3 Cache @ 266 MHz
Data bus parity
Bank A: 32 MB soldered flash using two Intel StrataFlash devices.
Bank B: 8 MB soldered flash using two Intel StrataFlash devices.
Bank A/B Reset vector jumper selectable
Double-Bit-Error detect, Single-Bit-Error correct across 72 bits.
Up to 1.5 GB of DDR266 (133 MHz) SDRAM onboard memory
Provided by Marvell MV64360 System Memory Controller.
Provided by Marvell MV64360 System Memory Controller.
Provided by Marvell MV64360 System Memory Controller.
One local PCI/PCI-X bus supporting 32/64-bit, 33/66 MHz PCI or 66/133
MHz PCI-X to PMC2.
One local PCI bus supporting 32-bit, 33 MHz PCI to PMC 1, the 21555 PCI
bridge, and IDE controller.
Three Gigabit Ethernet channels provided by the Marvell MV64360
Two to J3 for PICMG 2.16 compliance
One to front panel
Two 8 KB dual-address I2C SEEPROM devices for Vital Product Data and
user configuration data
Industry standard SPD for onboard and mezzanine board memory.
Intel 21555 PCI-to-PCI Bridge
64-bit, 33/66 MHz PCI to CompactPCI bus
Peripheral Slot operation
Single slot 6U CompactPCI
32KB NVRAM/RTC/WDT provided by M48T37V
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