Low-Power-Mode Idd Measurement Principle - Logic Part; Figure 17. Schematic Diagram Of The Analog Part Of Idd Measurement - STMicroelectronics STM32L476G-EVAL User Manual

Hardware layout and configuration
bypass path
2.30.2

Low-power-mode IDD measurement principle - logic part

The target microcontroller can only carry out actions for measuring a voltage when in
dynamic run mode. This is the reason why, voltage representing the current consumed by
the microcontroller when in low-power mode needs to be held by a sample-and-hold circuit,
for being exploited by the microcontroller at a later time, when back in dynamic run mode.
The sample-and-hold (S&H) circuit is built with U13 switch, R122 resistor and C73 sampling
capacitor.
The measurement of low-power-mode current consumption is started and end by the
microcontroller in its dynamic run mode. As, between the start and end event, the
microcontroller must transit through one of its low-power modes, an extra logic is required to
time and control events during this state. It consists of U14 counter, U16 inverter and the
transistor T3.
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Figure 17. Schematic diagram of the analog part of IDD measurement

VDD from
power
supply
VDD
Current
direction
T2
4
Shunt_x1000 3 5
1
2
6
FDC606P
current
measurement
path
JP11
Current
direction
Figure 18 shows the corresponding schematic diagram.
U15B
TSZ124IPT
5
R136
7
6
3K6 0.1%
R135
1[1%]
shunts
R123
1K[1%]
differential
amplifier
U15D
TSZ124IPT
12
R125
14
13
3K6 0.1%
VDD_MCU
to MCU
DocID027351 Rev 3
+5V
decoupling capacitor
C75
close from TSZ124 part
100nF
R128
22K U15A
GND
TSZ124IPT
3
1
V+
R124
2
V-
C144 1K
100nF
GND
GND GND
R129
180K 0.1%
U15C
10 TSZ124IPT
8
9
R132
180K 0.1%
UM1855