Hardware layout and configuration
LCD
segment
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG10
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Figure 10. LCD glass module daughterboard in I/O-bridge position
Table 14. LCD-daughterboard-related configuration elements
Setting to enable
Element
LCD glass
module
R82
In
SB32
Open
R81
In
SB31
Open
R78
In
SB22
Open
R68
In
SB21
Open
SB20
Open
R66
In
SB18
Open
SB19
Open
R62
In
SB14
Open
SB15
Open
R56
In
SB12
Open
SB13
Open
R50
In
SB9
Open
DocID027351 Rev 3
Description
PA1 routed to LCDSEG0
PA1 not routed to motor control
PA2 routed to LCDSEG1
PA2 not routed to motor control
PA3 routed to LCDSEG2
PA3 not routed to motor control
PA6 routed to LCDSEG3
PA6 not routed to Quad-SPI Flash memory device
PA6 not routed to motor control
PA7 routed to LCDSEG4
PA7 not routed to Quad-SPI Flash memory device
PA7 not routed to motor control
PB0 routed to LCDSEG5
PB0 not routed to Quad-SPI Flash memory device
PB0 not routed to motor control
PB1 routed to LCDSEG6
PB1 not routed to Quad-SPI Flash memory device
PB1 not routed to motor control
PB10 routed to LCDSEG10
PB10 not routed to Quad-SPI Flash memory device
UM1855
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