Intel iAPX 86/88 User Manual page 61

IDENTIFIER
MOD
REG
R/M
SR
W,S, 0, V,Z
DATA-S
DATA-SX
DATA-LO
DATA-HI
(OISP-LO)
(OISP-HI)
IP-LO
IP-HI
CS-LO
CS-HI
IP-INCS
IP-INC-LO
IP-INC-HI
AOOR-LO
AOOR-HI
xxx
YYY
REGS
REG16
MEMS
MEM16
IMMEOS
IMME016
SEGREG
OEST-STRS
8086/8088 CPU
Table 1-21 Key to Machine Instruction Encoding and Decoding
EXPLANATION
Mode field; described in this chapter.
Register field; described in this chapter.
Register/Memory field; described in this chapter.
Segment register code: OO=ES, 01=CS, 10=SS, 11 =OS.
Single-bit instruction fields; described in this chapter.
S-bit immediate constant.
8-bit immediate value that is automatically sign-extended to 16-bits
before use.
Low-order byte of 16-bit immediate constant.
High-order byte of 16-bit immediate constant.
Low-order byte of optional S- or 16-bit unsigned displacement; MOD
indicates if present.
High-order byte of optional 16-bit unsigned displacement; MOD
indicates if present.
Low-order byte of new IP value.
High-order byte of new IP value
Low-order byte of new CS value.
High-order byte of new CS value.
S-bit signed increment to instruction pointer.
Low-order byte of signed 16-bit instruction pointer increment.
High-order byte of signed 16-bit instruction pointer increment.
Low-order byte of direct address (offset) of memory operand; EA not
calculated.
High-order byte of direct address (offset) of memory operand; EA not
calculated.
Bits may contain any value.
First 3 bits of ESC opcode.
Second 3 bits of ESC opcode.
S-bit general register operand.
16-bit general register operand.
S-bit memory operand (any addressing mode).
16-bit memory operand (any addressing mode).
S-bit immediate operand.
16-bit immediate operand.
Segment register operand.
Byte string addressed by 01.
1-45
210912-001