Intel Quad-Core Xeon 3300 Series Datasheet
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Intel Quad-Core Xeon 3300 Series Datasheet

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Quad-Core Intel® Xeon® Processor
3300 Series
Datasheet
February 2009
Version -002
Document Number: 319005-002

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Summary of Contents for Intel Quad-Core Xeon 3300 Series

  • Page 1 Quad-Core Intel® Xeon® Processor 3300 Series Datasheet February 2009 Version -002 Document Number: 319005-002...
  • Page 2 Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information. Intel, Pentium, Xeon, Intel Core, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others.

  • Page 3: Table Of Contents

    Contents Introduction ......................9 Terminology ....................... 9 1.1.1 Processor Terminology Definitions ............10 References ....................... 11 Electrical Specifications ................... 13 Power and Ground Lands..................13 Decoupling Guidelines ..................13 2.2.1 Vcc Decoupling ..................13 2.2.2 Vtt Decoupling ..................13 2.2.3 FSB Decoupling..................
  • Page 4 Stop Grant Snoop State................89 6.2.4.1 HALT Snoop State, Stop Grant Snoop State ........90 6.2.4.2 Extended HALT Snoop State ............90 ® 6.2.5 Enhanced Intel SpeedStep Technology ............90 6.2.6 Processor Power Status Indicator (PSI) Signal ..........90 Boxed Processor Specifications................91 Introduction ......................91 Mechanical Specifications ..................92 7.2.1...
  • Page 5 Processor Land Coordinates and Quadrants, Top View..........40 land-out Diagram (Top View – Left Side)..............42 land-out Diagram (Top View – Right Side)............... 43 ® Xeon® Processor 3300 Series Quad-Core Intel Thermal Profile(95W) ........ 78 ® ® Quad-Core Intel Xeon Processor 3300 Series Thermal Profile (65W) .......

  • Page 6: Revision History

    Revision History Document Version Revision Revision Description Number Number Date January 319005 -001 • Initial release 2008 • Added Quad-Core Intel® Xeon® Processor X3380 & L3360 February -002 • Updated VID information 2009 • Added PSI# Signal Datasheet...
  • Page 7 Intel 64 architecture enables the processor to execute operating systems and applications written to ® take advantage of the Intel 64 architecture. The processor, supporting Enhanced Intel Speedstep technology, allows tradeoffs to be made between performance and power consumption. ®...
  • Page 8 Datasheet...

  • Page 9: Introduction

    775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. Note: In this document the Quad-Core Intel® Xeon® Processor 3300 Series may be referred to simply as "the processor." Note: The Quad-Core Intel® Xeon® Processor 3300 Series refers to X3380, X3360, X3350, X3330, X3320, L3360.

  • Page 10: Processor Terminology Definitions

    Processor Terminology Definitions Commonly used terms are explained here for clarification: • Quad-Core Intel® Xeon® Processor 3300 Series — Quad core processor in the FC-LGA6 package with two 6 MB L2 cache or two 3 B L2 cache. • Processor — For this document, the term processor is the generic form of the Quad-Core Intel®...

  • Page 11: References

    Introduction solutions and enables more robust hardware assisted virtualization solutions. More information can be found at: http://www.intel.com/technology/virtualization/ • Platform Environment Control Interface (PECI) — A proprietary one-wire bus interface that provides a communication channel between the processor and chipset components to external monitoring devices.
  • Page 12 Introduction Datasheet...

  • Page 13: Electrical Specifications

    Electrical Specifications Electrical Specifications Power and Ground Lands The processor has VCC (power), VTT, and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V , while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands.

  • Page 14: Voltage Identification

    Specification Update for further details on specific valid core frequency and VID values of the processor. Note that this differs from the VID employed by the processor during ® a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep technology, or Extended HALT State). The processor uses...
  • Page 15 Electrical Specifications Voltage Voltage 1.525 0.95 1.5125 0.9375 0.925 1.4875 0.9125 1.475 1.4625 0.8875 1.45 0.875 1.4375 0.8625 1.425 0.85 1.4125 0.8375 0.825 1.3875 0.8125 1.375 1.3625 0.7875 1.35 0.775 1.3375 0.7625 1.325 0.75 1.3125 0.7375 0.725 1.2875 0.7125 1.275 1.2625 0.6875 1.25...

  • Page 16: Reserved, Unused, And Testhi Signals

    Electrical Specifications Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to V or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.

  • Page 17: Power Segment Identifier (Psid)

    Electrical Specifications Power Segment Identifier (PSID) Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched power requirement situations. The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator (VR) is capable of supplying.

  • Page 18: Dc Voltage And Current Specification

    Electrical Specifications Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications. This rating applies to the processor and does not include any tray or packaging. Failure to adhere to this specification can affect the long term reliability of the processor. 2.7.2 DC Voltage and Current Specification Table 2-3.

  • Page 19: V Static And Transient Tolerance

    Electrical Specifications different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel ® SpeedStep Technology, or Extended HALT State). Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.

  • Page 20: Vcc Static And Transient Tolerance

    Electrical Specifications Table 2-4. Static and Transient Tolerance (Continued) 1, 2, 3, 4 Voltage Deviation from VID Setting (V) Maximum Voltage Typical Voltage Minimum Voltage 1.30 mΩ 1.38 mΩ 1.45 mΩ -0.111 -0.136 -0.161 -0.117 -0.143 -0.169 -0.124 -0.150 -0.176 -0.130 -0.157 -0.183...

  • Page 21: Vcc Overshoot

    Electrical Specifications The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details.

  • Page 22: Die Voltage Validation

    Termination resistors (R ) for GTL+ signals are provided on the processor silicon and are terminated to V . Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.

  • Page 23: Fsb Signal Groups

    Electrical Specifications Table 2-6. FSB Signal Groups Signal Group Type Signals GTL+ Common Synchronous to BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# Clock Input BCLK[1:0] GTL+ Common Synchronous to ADS#, BNR#, BPM[5:0]#, BPMb[3:0]#, BR0# , DBSY#, Clock I/O BCLK[1:0] DRDY#, HIT#, HITM#, LOCK# Signals Associated Strobe REQ[4:0]#, A[16:3]#...

  • Page 24: Cmos And Open Drain Signals

    Electrical Specifications Table 2-7. Signal Characteristics Signals with R Signals with No R A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0], FERR#/PBE#, IERR#, IGNNE#, A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/ D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, NMI, MSID[1:0], PWRGOOD, RESET#, SMI#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, STPCLK#, TDO, TDO_M, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, TESTHI[13,11:10,7:0], THERMTRIP#,...

  • Page 25: Open Drain And Tap Output Signal Group Dc Specifications

    Electrical Specifications Table 2-9. GTL+ Signal Group DC Specifications Symbol Parameter Unit Notes Input Leakage ± 100 µA Current Output Leakage ± 100 µA Current Buffer On Resistance 7.49 9.16 Ω NOTES: Unless otherwise noted, all specifications in this table apply to all processor frequencies. is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

  • Page 26: Platform Environment Control Interface (Peci) Dc Specifications

    2.8.3.1 Platform Environment Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors, chipsets, and external thermal monitoring devices. The Yorkfield processor contains Digital Thermal Sensors (DTS) distributed throughout die.

  • Page 27: Gtl+ Bus Voltage Definitions

    Electrical Specifications Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 2-13 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.

  • Page 28: Clock Specifications

    13.5, refer to Table 2-14 for the processor supported ratios. The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Table 2-14. Core Frequency to FSB Multiplier Configuration Multiplication of Core Frequency...

  • Page 29: Fsb Frequency Select Signals (Bsel[2:0])

    Electrical Specifications The Yorkfield processor will operate at a 1333 MHz FSB frequency (selected by a 333 MHz BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency. For more information about these signals, refer to Section 4.2 and the appropriate platform design guidelines.

  • Page 30: Bclk[1:0] Specifications

    Electrical Specifications 2.9.4 BCLK[1:0] Specifications Table 2-16. Front Side Bus Differential BCLK Specifications Symbol Parameter Unit Figure Notes Input Low Voltage -0.30 Input High Voltage 1.15 Absolute Crossing 0.300 0.550 Point CROSS(abs) Range of Crossing ∆V 0.140 Points CROSS Overshoot Undershoot -0.300 Differential Output...

  • Page 31: Differential Clock Waveform

    Electrical Specifications Duty Cycle (High time/Period) must be between 40 and 60% Figure 2-3. Differential Clock Waveform Overshoot BCLK1 Rising Edge Ringback Ringback Margin Threshold CROSS (ABS CROSS (ABS Region Falling Edge Ringback BCLK0 Undershoot Tp = T1: BCLK[1:0] period T2: BCLK[1:0] period stability (not shown) Tph = T3: BCLK[1:0] pulse high time Tpl = T4: BCLK[1:0] pulse low time...
  • Page 32 Electrical Specifications Datasheet...

  • Page 33: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA8) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.

  • Page 34: Package Mechanical Drawing

    Package Mechanical Specifications 3.1.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3-2 Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: 1. Package reference with tolerances (total height, length, width, etc.) 2.

  • Page 35: Processor Package Drawing Sheet 1 Of 3

    Package Mechanical Specifications Figure 3-2. Processor Package Drawing Sheet 1 of 3 Datasheet...

  • Page 36: Processor Package Drawing Sheet 2 Of 3

    Package Mechanical Specifications Figure 3-3. Processor Package Drawing Sheet 2 of 3 Datasheet...

  • Page 37: Processor Package Drawing Sheet 3 Of 3

    Package Mechanical Specifications Figure 3-4. Processor Package Drawing Sheet 3 of 3 Datasheet...

  • Page 38: Processor Component Keep-Out Zones

    Package Mechanical Specifications 3.1.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate.

  • Page 39: Package Insertion Specifications

    3.1.8 Processor Markings Figure 3-5 shows the topside markings on the processor. This diagram is to aid in the identification of the processor. Figure 3-5. Processor Top-Side Markings Example INTEL ©'06 3360 INTEL® XEON® SLxxx [COO] 2.83GHZ/12M/1333/05A [FPO] ATPO Datasheet...

  • Page 40: Processor Land Coordinates

    Package Mechanical Specifications 3.1.9 Processor Land Coordinates Figure 3-6 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Figure 3-6. Processor Land Coordinates and Quadrants, Top View Address/ Socket 775 Common Clock/ Quadrants...

  • Page 41: Land Listing And Signal Descriptions

    Land Listing and Signal Descriptions Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown Figure 4-1 Figure 4-2.

  • Page 42: Land-Out Diagram (Top View - Left Side)

    Land Listing and Signal Descriptions Figure 4-1.land-out Diagram (Top View – Left Side) FC34 FC31 BSEL1 FC15 FC33 FC32 BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD D43# D41#...

  • Page 43: Land-Out Diagram (Top View - Right Side)

    Land Listing and Signal Descriptions Figure 4-2.land-out Diagram (Top View – Right Side) VID_SEL VSS_MB_ VCC_MB_ VSS_ VCC_ REGULATION REGULATION SENSE SENSE VID7 FC40 VID6 VID2 VID0 VID3 VID1 VID5 VRDSEL PROCHOT# FC25 VID4 ITP_CLK0 FC24 A35# A34# ITP_CLK1 BPM0# BPM1# A33# A32#...

  • Page 44: Alphabetical Land Assignments

    Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type A10# Source Synch Input/Output BNR# Common Clock Input/Output A11# Source Synch Input/Output BPM0#...
  • Page 45 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type D25# Source Synch Input/Output D60# Source Synch Input/Output D26# Source Synch Input/Output D61#...
  • Page 46 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type FC32 Power/Other RESERVED FC33 Power/Other RESERVED FC34 Power/Other RESERVED FC35 Power/Other RESERVED...
  • Page 47 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type TRDY# Common Clock Input AF22 Power/Other TRST# Input Power/Other Power/Other Power/Other Power/Other...
  • Page 48 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type AJ18 Power/Other AM19 Power/Other AJ19 Power/Other AM21 Power/Other AJ21 Power/Other AM22 Power/Other...
  • Page 49 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 50 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type VID0 Asynch CMOS Output AB26 Power/Other VID1 Asynch CMOS Output AB27 Power/Other...
  • Page 51 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type AF30 Power/Other Power/Other Power/Other AK20 Power/Other Power/Other AK23 Power/Other AG10 Power/Other AK24...
  • Page 52 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type AN24 Power/Other Power/Other AN27 Power/Other Power/Other AN28 Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 53 Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Table 4-1. Alphabetical Land Assignments Assignments Signal Buffer Signal Buffer Land Name Land # Direction Land Name Land # Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other VSS_MB_ Power/Other Output...
  • Page 54 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D08# Source Synch Input/Output AA30 Power/Other D09# Source Synch Input/Output A21# Source Synch Input/Output Power/Other...
  • Page 55 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type BPM2# Common Clock Input/Output RESERVED AD23 Power/Other Power/Other AD24 Power/Other RESERVED AD25 Power/Other Power/Other...
  • Page 56 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AG12 Power/Other AH20 Power/Other AG13 Power/Other AH21 Power/Other AG14 Power/Other AH22 Power/Other AG15 Power/Other...
  • Page 57 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AJ29 Power/Other FC25 Power/Other ITP_CLK1 Input AL10 Power/Other AJ30 Power/Other AL11 Power/Other Power/Other AL12...
  • Page 58 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type AM18 Power/Other AN26 Power/Other AM19 Power/Other AN27 Power/Other VID0 Asynch CMOS Output AN28 Power/Other...

  • Page 59: Numerical Land Assignment

    Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type D05# Source Synch Input/Output RESERVED D06# Source Synch Input/Output Power/Other Power/Other RESERVED DSTBP0# Source Synch...
  • Page 60 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type RESERVED Power/Other FC10 Power/Other D17# Source Synch Input/Output Power/Other D18# Source Synch Input/Output Power/Other BPMb0#...
  • Page 61 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type FC32 Power/Other Power/Other FC33 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other GTLREF1 Power/Other...
  • Page 62 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other TESTHI11 Power/Other Input Power/Other SMI# Asynch CMOS Input A06# Source Synch Input/Output...
  • Page 63 Land Listing and Signal Descriptions Table 4-2. Numerical Land Table 4-2. Numerical Land Assignment Assignment Land Signal Buffer Land Signal Buffer Land Name Direction Land Name Direction Type Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other MSID0 Power/Other Output Power/Other TDI_M Power/Other Input...

  • Page 64: Alphabetical Signals Reference

    Land Listing and Signal Descriptions Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 10) Name Type Description A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information.
  • Page 65 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 10) Name Type Description BPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance.
  • Page 66 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 10) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer.
  • Page 67 D[63:48]#, DBI3# DSTBP3# FC0/BOOTSELECT is not used by the Yorkfield processor. When this FC0/ land is tied to Vss previous processors based on the Intel NetBurst® Other BOOTSELECT microarchitecture should be disabled and prevented from booting. Refer to appropriate platform design guide for termination guidance.
  • Page 68 When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating- point error reporting.
  • Page 69 FSB throughout the bus locked operation and ensure the atomicity of lock. On a Yorkfield processor these signals are not connected on the package (they are floating). As an alternative to MSID, Intel has MSID[1:0] Output implemented the Power Segment Identifier (PSID) to report the maximum Thermal Design Power of the processor.
  • Page 70 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 10) Name Type Description PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
  • Page 71 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 10) Name Type Description STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.
  • Page 72 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 9 of 10) Name Type Description VCC are the power pins for the processor. The voltage supplied to Input these pins is determined by the VID[7:0] pins. VCCA provides isolated power for internal PLLs on previous VCCA Input generation processors.
  • Page 73 Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 10 of 10) Name Type Description The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to VTT_OUT_LEFT provide a voltage supply for some signals that require termination to Output on the motherboard. Refer to the appropriate platform design VTT_OUT_RIGHT guide for details on implementation.
  • Page 74 Land Listing and Signal Descriptions Datasheet...

  • Page 75: Thermal Specifications And Design Considerations

    5.1.1 Thermal Specifications To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T...

  • Page 76: Processor Thermal Specifications

    The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption.
  • Page 77 Thermal Specifications and Design Considerations ® ® Table 5-2. Quad-Core Intel Xeon Processor 3300 Series Thermal Profile (95W) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 44.8 58.8 45.4 59.4 45.9 59.9 46.5 60.5 47.0 61.0 47.6 61.6 48.2...

  • Page 78: Quad-Core Intel

    Thermal Specifications and Design Considerations ® ® Figure 5-1. Quad-Core Intel Xeon Processor 3300 Series Thermal Profile(95W) 72.0 68.0 64.0 y = 0.28x + 44.8 60.0 56.0 52.0 48.0 44.0 Power (W) Datasheet...

  • Page 79: Quad-Core Intel Xeon Processor 3300 Series Thermal Profile (65W)

    Thermal Specifications and Design Considerations ® ® Table 5-3. Quad-Core Intel Xeon Processor 3300 Series Thermal Profile (65W) Maximum Tc Maximum Tc Power (W) Power (W) (°C) (°C) 49.6 63.54 50.42 64.36 51.24 65.18 52.06 52.88 66.82 53.7 67.64 54.52 68.46...

  • Page 80: Thermal Metrology

    5-1. This temperature specification is meant to help ensure proper operation of the processor. Figure 5-3 illustrates where Intel recommends T thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum.

  • Page 81: Thermal Monitor 2

    Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.

  • Page 82: On-Demand Mode

    Thermal Specifications and Design Considerations Figure 5-4. Thermal Monitor 2 Frequency and Voltage Ordering Temperature Frequency PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode.

  • Page 83: Prochot# Signal

    5.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.

  • Page 84: Tcontrol And Tcc Activation On Peci-Based Systems

    Thermal Specifications and Design Considerations 5.3.1.1 and TCC activation on PECI-Based Systems CONTROL Fan speed control solutions based on PECI utilize a T value stored in the CONTROL processor IA32_TEMPERATURE_TARGET MSR. The T MSR uses the same offset CONTROL temperature format as PECI though it contains no sign bit. Thermal management devices should infer the T value as negative.

  • Page 85: Peci Gettemp0() Error Code Support

    Thermal Specifications and Design Considerations that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is know to be unresponsive. Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to provide reliable thermal data.
  • Page 86 Thermal Specifications and Design Considerations Datasheet...

  • Page 87: Features

    Features Features Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.

  • Page 88: Normal State

    LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume 3B: System Programming Guide, Part 2 for more information.

  • Page 89: Extended Halt Powerdown State

    Features The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed...

  • Page 90: Halt Snoop State, Stop Grant Snoop State

    Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology. This technology enables the processor to switch between frequency and voltage points, which may result in platform power savings. In order to support this technology, the system must support dynamic VID transitions.

  • Page 91: Boxed Processor Specifications

    Boxed Processor Specifications Introduction The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.

  • Page 92: Mechanical Specifications

    Boxed Processor Specifications Mechanical Specifications 7.2.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.

  • Page 93: Top View Space Requirements For The Boxed Processor

    Boxed Processor Specifications Figure 7-3. Top View Space Requirements for the Boxed Processor 95.0 [3.74] 95.0 [3.74] Boxed_Proc_TopView NOTES: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 7-4. Overall View Space Requirements for the Boxed Processor Datasheet...

  • Page 94: Boxed Processor Fan Heatsink Weight

    Boxed Processor Specifications 7.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Yorkfield Processor Thermal and Mechanical Design Guidelines Addendum for details on the processor weight and heatsink requirements. 7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly...

  • Page 95: Boxed Processor Fan Heatsink Power Cable Connector Description

    Boxed Processor Specifications Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description Signal Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. +12 V 0.100" pitch, 0.025" square pin width. SENSE CONTROL Match with straight pin, friction lock header on mainboard.

  • Page 96: Thermal Specifications

    Boxed Processor Specifications Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] Boxed_Proc_PwrHeaderPlacement Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.

  • Page 97: Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)

    Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Datasheet...

  • Page 98: Variable Speed Fan

    Boxed Processor Specifications Figure 7-8. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view) 7.4.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures.

  • Page 99: Boxed Processor Fan Heatsink Set Points

    As processor power has increased the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage.
  • Page 100 Boxed Processor Specifications If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard CPU fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet.

  • Page 101: Debug Tools Specifications

    Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Yorkfield processor systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature.
  • Page 102 Debug Tools Specifications Datasheet...

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