Intel Xeon Datasheet
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Intel Xeon Datasheet

Intel Xeon Datasheet

Processor with 800 mhz system bus
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Intel® Xeon™ Processor with 800 MHz
System Bus
Datasheet

Product Features

Available at 2.80, 3, 3.20, 3.40, 3.60 GHz
■
90 nm process technology
■
Dual processing server/workstation support
■
Binary compatible with applications
■
running on previous members of Intel's
IA-32 microprocessor line
■
Intel® NetBurst™ micro-architecture
■
Hyper-Threading Technology
■
Hardware support for multithreaded
applications
■
Faster 800 MHz system bus
Rapid Execution Engine: Arithmetic Logic
■
Units (ALUs) run at twice the processor
core frequency
Hyper Pipelined Technology
■
Advanced Dynamic Execution
■
Very deep out-of-order execution
■
■
Enhanced branch prediction
■
Includes 16-KB Level 1 data cache
The Intel® Xeon™ processor with 800 MHz system bus is designed for high-performance
dual-processor workstation and server applications. Based on the Intel® NetBurst™ micro-
architecture and the Hyper-Threading Technology, it is binary compatible with previous Intel
Architecture (IA-32) processors. The Intel Xeon processor with 800 MHz system bus is scalable
to two processors in a multiprocessor system providing exceptional performance for applications
running on advanced operating systems such as Windows XP*, Windows Server* 2003, Linux*,
and UNIX*.
The Intel Xeon processor with 800 MHz system bus
delivers compute power at unparalleled value and
flexibility for powerful workstations, internet
infrastructure, and departmental server applications. The
Intel NetBurst micro-architecture and Hyper-Threading
Technology deliver outstanding performance and
headroom for peak internet server workloads, resulting in
faster response times, support for more users, and
improved scalability.
Intel® Extended Memory 64 Technology
■
1-MB Advanced Transfer Cache (On-die,
■
full speed Level 2 (L2) Cache) with 8-way
associativity and Error Correcting Code
(ECC)
Enables system support of up to 64 GB of
■
physical memory
144 Streaming SIMD Extensions 2 (SSE2)
■
instructions
13 Streaming SIMD Extensions 3 (SSE3)
■
instructions
Enhanced floating-point and multimedia
■
unit for enhanced video, audio, encryption,
and 3D performance
■
System Management mode
■
Thermal Monitor
■
Machine Check Architecture (MCA)
■
Demand-Based Switching (DBS) with
Enhanced Intel SpeedStep® Technology
Document Number: 302355-001
June 2004

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Summary of Contents for Intel Xeon

  • Page 1: Product Features

    Based on the Intel® NetBurst™ micro- architecture and the Hyper-Threading Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The Intel Xeon processor with 800 MHz system bus is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP*, Windows Server* 2003, Linux*, and UNIX*.
  • Page 2 The Intel® Xeon™ processor with 800 MHz system bus may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

  • Page 3: Table Of Contents

    Processor Pinout Coordinates .................... 37 Signal Definitions ........................39 Signal Definitions ........................ 39 Pin List............................49 Intel® Xeon™ Processor with 800 MHz System Bus Pin Assignments ......49 5.1.1 Pin Listing by Pin Name..................50 5.1.2 Pin Listing by Pin Number ..................58...
  • Page 4 Stop-Grant State....................76 7.2.4 HALT Snoop State or Snoop State................ 77 7.2.5 Sleep State ......................77 Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technology ....78 Boxed Processor Specifications....................79 Introduction ......................... 79 Mechanical Specifications ....................81 8.2.1 Boxed Processor Heatsink Dimensions (CEK)............81 8.2.2...
  • Page 5 Figures Phase Lock Loop (PLL) Filter Requirements ................15 Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.0)..25 Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.1)..25 VCC Static and Transient Tolerance..................27 VCC Overshoot Example Waveform ..................
  • Page 6 Intel® Xeon™ Processor with 800 MHz System Bus Tables Features of the Intel® Xeon™ Processor with 800 MHz System Bus ........10 Core Frequency to Front Side Bus Multiplier Configuration ............14 BSEL[1:0] Frequency Table ....................... 14 Voltage Identification Definition 2,3.................... 16 Front Side Bus Signal Groups....................

  • Page 7: Revision History

    Intel® Xeon™ Processor with 800 MHz System Bus Revision History Date Revision Description June 2004 Initial release. Datasheet...
  • Page 8 Intel® Xeon™ Processor with 800 MHz System Bus Datasheet...

  • Page 9: Introduction

    Intel® Xeon™ Processor with 800 MHz System Bus Introduction The Intel® Xeon™ processor with 800 MHz system bus is a 32-bit server / workstation processor based on improvements to the Intel NetBurst® microarchitecture. It maintains the tradition of compatibility with IA-32 software and includes features found in the Intel® Xeon™ processor such as Hyper Pipelined Technology, a Rapid Execution Engine, and an Execution Trace Cache.

  • Page 10: Terminology

    Guidelines or Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines) for further details. The Intel® Xeon™ processor with 800 MHz system bus uses a scalable system bus protocol referred to as the “system bus” in this document. The system bus uses a split-transaction, deferred reply protocol.
  • Page 11 IHS surface. • mPGA604 Socket — The Intel® Xeon™ processor with 800 MHz system bus mates with the baseboard through this surface mount, 604-pin, zero insertion force (ZIF) socket. See the mPGA604 Socket Design Guidelines for details regarding this socket.

  • Page 12: References

    Intel® Xeon™ Processor with 800 MHz System Bus Mechanical Models (ProE*) zip file Intel® Xeon™ Processor with 800 MHz System Bus Thermal / Mechanical Design Guide 302404 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 302731 Design Guidelines Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1...

  • Page 13: Electrical Specifications

    Table Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the Intel® Xeon™ processor with 800 MHz system bus is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.

  • Page 14: Front Side Bus Clock (Bclk[1:0]) And Processor Clocking

    BCLK[1:0] directly controls the front side bus interface speed as well as the core frequency of the processor. As in previous processor generations, the Intel® Xeon™ processor with 800 MHz system bus core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set during manufacturing.

  • Page 15: Phase Lock Loop (Pll) And Filter

    2.3.2 Phase Lock Loop (PLL) and Filter and V are power sources required by the PLL clock generators on the Intel® Xeon™ CCIOPLL processor with 800 MHz system bus. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency).

  • Page 16: Voltage Identification Definition 2,3

    Guidelines or Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines for further details. The Intel® Xeon™ processor with 800 MHz system bus provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V ).

  • Page 17: Reserved Or Unused Pins

    1. When this VID pattern is observed, the voltage regulator output should be disabled. 2. Shading denotes the expected default VID range during normal operation for Intel® Xeon™ processor with 800 MHz system bus [1.2875 V -1.4000 V]. Please note this is subject to change.

  • Page 18: Front Side Bus Signal Groups

    N/C (no connect) pins of the processor are not used by the processor. There is no connection from the pin to the die. These pins may perform functions in future processors intended for platforms using the Intel® Xeon™ processor with 800 MHz system bus. Front Side Bus Signal Groups The front side bus signals have been combined into groups by buffer type.

  • Page 19: Front Side Bus Signal Groups

    1. Refer to Section 4.0 for signal descriptions. 2. The Intel® Xeon™ processor with 800 MHz system bus only uses BR0# and BR1#. BR2# and BR3# must be terminated to V . For additional details regarding the BR[3:0]# signals, see Section 4.0...

  • Page 20: Gtl+ Asynchronous And Agtl+ Asynchronous Signals

    GTL+ Asynchronous and AGTL+ Asynchronous Signals The Intel® Xeon™ processor with 800 MHz system bus does not use CMOS voltage levels on any signals that connect to the processor silicon. As a result, input signals such as A20M#,...

  • Page 21: Test Access Port (Tap) Connection

    Mixing processors of different steppings but the same model (as per CPUID instruction) is supported. Please see the Intel® Xeon™ Processor with 800 MHz System Bus Specification Update for the applicable mixed stepping table. Details regarding the CPUID instruction are provided in the Intel®...

  • Page 22: Processor Dc Specifications

    The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Intel® Xeon™ processor with 800 MHz system bus will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not have specifications equal to the FMB value in the foreseeable future.

  • Page 23: Voltage And Current Specifications

    Intel® Xeon™ Processor with 800 MHz System Bus Table 9. Voltage and Current Specifications Symbol Parameter Unit Notes VID range VID range for Intel® Xeon™ 1.2875 1.4000 processor with 800 MHz system bus for Intel® Xeon™ processor Table 10 VID - I (max) * 1.25 mΩ...
  • Page 24 Intel® Xeon™ Processor with 800 MHz System Bus 7. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See Section 2.11.1 for further details on FMB guidelines. 8. This specification represents the V reduction due to each VID transition. See Section 2.4.

  • Page 25: Intel® Xeon™ Processor With 800 Mhz System Bus Load Current Vs. Time (Vrm 10.0)

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 2. Intel® Xeon™ Processor with 800 MHz System Bus Load Current vs. Time (VRM 10.0) V RM 10.0 Current 0.01 1000 Time Du ra tio n (s ) NOTES: 1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than CC_TDC 2.

  • Page 26: Vcc Static And Transient Tolerance

    Intel® Xeon™ Processor with 800 MHz System Bus Table 10. Static and Transient Tolerance 1,2,3 Voltage Deviation from VID Setting (V) CC_Max CC_Typ CC_Min VID - 0.000 VID - 0.020 VID - 0.040 VID - 0.006 VID - 0.026 VID - 0.046 VID - 0.013...

  • Page 27: Vcc Overshoot Specification

    Voltage Regulator Down (EVRD) 10.1 Design Guidelines for socket loadline guidelines and VR implementation. 2.11.2 Overshoot Specification The Intel® Xeon™ processor with 800 MHz system bus can tolerate short transient overshoot events where V exceeds the VID voltage when transitioning from a high-to-low current load condition.

  • Page 28: Die Voltage Validation

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 5. Overshoot Example Waveform VID + 0.050 VID - 0.000 Time [us] : Overshoot time above VID : Overshoot above VID NOTES: 1. V is measured overshoot voltage. 2. T is measured time duration above VID.

  • Page 29: Agtl+ Signal Group Dc Specifications

    Intel® Xeon™ Processor with 800 MHz System Bus Table 13. AGTL+ Signal Group DC Specifications Symbol Parameter Unit Notes Input Low Voltage GTLREF - (0.10 * V Input High Voltage GTLREF + 2,4,5 (0.10 * V Output High Voltage 0.90 * V Output Low Current (0.50 * R...

  • Page 30: Gtl+ Asynchronous And Agtl+ Asynchronous Signal Group Dc Specifications

    Intel® Xeon™ Processor with 800 MHz System Bus Table 15. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC Specifications Symbol Parameter Unit Notes Input Low Voltage GTLREF - (0.10 * V Input High Voltage GTLREF + (0.10 * V 2,4,5 Output High Voltage 0.90 * V...

  • Page 31: Mechanical Specifications

    Intel® Xeon™ Processor with 800 MHz System Bus Mechanical Specifications The Intel® Xeon™ processor with 800 MHz system bus is packaged in Flip Chip Micro Pin Grid Array (FC-mPGA4) package that interfaces to the baseboard via an mPGA604 socket. The package consists of a processor core mounted on a substrate pin-carrier.

  • Page 32: Processor Package Drawing (Sheet 1 Of 2)

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 7. Processor Package Drawing (Sheet 1 of 2) Datasheet...

  • Page 33: Processor Package Drawing (Sheet 2 Of 2)

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 8. Processor Package Drawing (Sheet 2 of 2) Datasheet...

  • Page 34: Processor Component Keepout Zones

    Intel® Xeon™ Processor with 800 MHz System Bus Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate.

  • Page 35: Package Handling Guidelines

    Socket Design Guidelines. Processor Mass Specifications The typical mass of the Intel® Xeon™ processor with 800 MHz system bus is 25 grams [0.88 oz.]. This mass [weight] includes all components which make up the entire processor product. Processor Materials The Intel®...

  • Page 36: Processor Markings

    Figure 9 shows the topside markings and Figure 10 shows the bottom-side markings on the processor. These diagrams are to aid in the identification of the Intel® Xeon™ processor with 800 MHz system bus. Figure 9. Processor Top-Side Markings (Example)

  • Page 37: Processor Pinout Coordinates

    Intel® Xeon™ Processor with 800 MHz System Bus Processor Pinout Coordinates Figure 11 Figure 12 show the top and bottom view of the processor pin coordinates, respectively. The coordinates are referred to throughout the document to identify processor pins. Figure 11.

  • Page 38: Processor Pinout Coordinates, Bottom View

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 12. Processor Pinout Coordinates, Bottom View Async / COMMON COMMON ADDRESS JTAG CLOCK CLOCK Intel® Xeon™ Processor (800 MHz) Bottom View CLOCKS DATA = Signal = GTLREF = Power = Reserved/No Connect...

  • Page 39: Signal Definitions

    This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Intel® Xeon™ processor with 800 MHz system bus agents. The following table defines the coverage model of these signals.
  • Page 40 BOOT_ The BOOT_SELECT input informs the processor whether the platform supports the SELECT Intel® Xeon™ processor with 800 MHz system bus. The processor will not operate if this signal is low. This input has a weak pull-up to V BPM[5:0]# BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
  • Page 41 The required frequency is determined by the processors, chipset, and clock synthesizer. All front side bus agents must operate at the same frequency. The Intel® Xeon™ processor with 800 MHz system bus currently operates at a 800 MHz system bus frequency (200 MHz BCLK[1:0] frequency).
  • Page 42 Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Signal Definitions (Sheet 4 of 9) Name Type Description Notes DBI[3:0]# DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than...
  • Page 43 This signal does not have on-die termination and must be terminated at the end agent. FORCEPR# The FORCEPR# input can be used by the platform to force the Intel® Xeon™ processor with 800 MHz system bus to activate the Thermal Control Circuit (TCC). The TCC will remain active until the system deasserts FORCEPR#.
  • Page 44 Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Signal Definitions (Sheet 6 of 9) Name Type Description Notes LINT[1:0] LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side bus agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR, a maskable interrupt request signal, and LINT1/NMI becomes NMI, a nonmaskable interrupt.
  • Page 45 Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Signal Definitions (Sheet 7 of 9) Name Type Description Notes REQ[4:0]# REQ[4:0]# (Request Command) must connect the appropriate pins of all processor front side bus agents. They are asserted by the current bus owner to define the currently active transaction type.
  • Page 46 Intel® Xeon™ Processor with 800 MHz System Bus Table 20. Signal Definitions (Sheet 8 of 9) Name Type Description Notes TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.
  • Page 47 1. The Intel® Xeon™ processor with 800 MHz system bus only supports BR0# and BR1#. However, platforms must terminate BR2# and BR3# to V 2. For this pin on Intel® Xeon™ processor with 800 MHz system bus, the maximum number of symmetric agents is one. Maximum number of central agents is zero.
  • Page 48 Intel® Xeon™ Processor with 800 MHz System Bus Datasheet...

  • Page 49: Pin List

    Intel® Xeon™ Processor with 800 MHz System Bus Pin List Intel® Xeon™ Processor with 800 MHz System Bus Pin Assignments This section provides sorted pin lists in Table 21 Table Table 21 is a listing of all processor pins ordered alphabetically by pin name.

  • Page 50: Pin Listing By Pin Name

    Intel® Xeon™ Processor with 800 MHz System Bus 5.1.1 Pin Listing by Pin Name Table 21. Pin Listing by Pin Name (Sheet 1 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Source Sync AP1#...
  • Page 51 Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 2 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type D17# AC26 Source Sync D57# Source Sync D18# AD25...
  • Page 52 Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 3 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type MCERR# Common Clk Input Input AA28 Output AA29 TEST_BUS...
  • Page 53 Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 4 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 54 Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 5 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 55 Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 6 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type VCCPLL Power/Other Input Power/Other VCCSENSE Power/Other Output Power/Other VID0...
  • Page 56 Intel® Xeon™ Processor with 800 MHz System Bus Table 21. Pin Listing by Pin Name (Sheet 7 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 57 AA12 Power/Other AC13 Power/Other AC10 Power/Other AC19 Power/Other AD12 Power/Other AC25 Power/Other VTTEN Power/Other Output NOTE: In systems using the Intel® Xeon™ processor with 800 MHz system bus, the system designer must pull-up these signals to the processor V Datasheet...

  • Page 58: Pin Listing By Pin Number

    Intel® Xeon™ Processor with 800 MHz System Bus 5.1.2 Pin Listing by Pin Number Table 22. Pin Listing by Pin Number (Sheet 1 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type VID5 Power/Other Output...
  • Page 59 Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin Listing by Pin Number (Sheet 2 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type A15# Source Sync Power/Other Power/Other Reserved Reserved Reserved Source Sync...
  • Page 60 Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin Listing by Pin Number (Sheet 3 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Power/Other Power/Other VID0 Power/Other Output Power/Other Power/Other Power/Other BPM3#...
  • Page 61 Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin Listing by Pin Number (Sheet 4 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 62 Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin Listing by Pin Number (Sheet 5 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other...
  • Page 63 Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin Listing by Pin Number (Sheet 6 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type Power/Other DSTBP1# Source Sync Power/Other DSTBN1# Source Sync Power/Other...
  • Page 64 Intel® Xeon™ Processor with 800 MHz System Bus Table 22. Pin Listing by Pin Number (Sheet 7 of 8) Signal Signal Pin Name Direction Pin Name Direction Buffer Type Buffer Type AA26 Power/Other Power/Other AA27 Source Sync D60# Source Sync...
  • Page 65 Reserved Reserved Reserved TESTHI6 Power/Other Input AE29 Reserved Reserved Reserved SLP# Async GTL+ Input AE30 NOTE: In systems using the Intel® Xeon™ processor with 800 MHz system bus, the system designer must pull-up these signals to the processor V Datasheet...
  • Page 66 Intel® Xeon™ Processor with 800 MHz System Bus Datasheet...

  • Page 67: Thermal Specifications

    Thermal Specifications Package Thermal Specifications The Intel® Xeon™ processor with 800 MHz system bus requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.

  • Page 68: Intel® Xeon™ Processor With 800 Mhz System Bus Thermal Specifications

    Intel® Xeon™ Processor with 800 MHz System Bus will violate the thermal specifications and may result in permanent damage to the processor. Intel has developed these thermal profiles to allow OEMs to choose the thermal solution and environmental parameters that best suit their platform implementation. Refer to the appropriate thermal/mechanical design guide for details on system thermal solution design, thermal profiles, and environmental considerations.

  • Page 69: Intel® Xeon™ Processor With 800 Mhz System Bus Thermal Profiles A And B

    Furthermore, usage of thermal solutions that do not meet Thermal Profile B do not meet the processor’s thermal specifications and may result in permanent damage to the processor. 5. Refer to the Intel® Xeon™ Processor with 800 MHz System Bus Thermal/Mechanical Design Guidelines for system and environmental implementation details.

  • Page 70: Intel® Xeon™ Processor With 800 Mhz System Bus Thermal Profile A

    Intel® Xeon™ Processor with 800 MHz System Bus Table 24. Intel® Xeon™ Processor with 800 MHz System Bus Thermal Profile A Power [W] [°C] Power [W] [°C] CASE_MAX CASE_MAX = 25 CONTROL_BASE_A Table 25. Intel® Xeon™ Processor with 800 MHz System Bus Thermal Profile B Power [W] [°C]...

  • Page 71: Thermal Metrology

    Intel® Xeon™ Processor with 800 MHz System Bus 6.1.2 Thermal Metrology The maximum case temperatures (T ) are specified in Table Table 25 and measured at the CASE geometric top center of the processor integrated heat spreader (IHS). Figure 14...

  • Page 72: On-Demand Mode

    The FORCEPR# (force power reduction) input can be used by the platform to cause the Intel® Xeon™ processor with 800 MHz system bus to activate the TCC. If the Thermal Monitor is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal. The TCC will remain active until the system deasserts FORCEPR#.

  • Page 73: Thermtrip# Signal Pin

    The base value is 50 °C. The value of Tcontrol may vary from 0x00h to 0x1Eh. Systems that support the Intel® Xeon™ processor with 800 MHz system bus must implement BIOS changes to detect which processor is present, and then select the appropriate Tcontrol_base value.

  • Page 74: Thermal Diode Interface

    Intel® Xeon™ Processor with 800 MHz System Bus 3. Not 100% tested. Specified by design characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode qVD/nkT equation: I * (e - 1)

  • Page 75: Features

    2. Address pins not identified in this table as configuration options should not be asserted during RESET#. 3. The Intel® Xeon™ processor with 800 MHz system bus only uses the BR0# and BR1# signals. Platforms must not use BR2# and BR3# signals.

  • Page 76: Normal State

    STPCLK# pin has been asserted, it may only be deasserted once the processor is in the state. For ° the Intel® Xeon™ processor with 800 MHz system bus, both logical processors must be in the ° state before the deassertion of STPCLK#.

  • Page 77: Halt Snoop State Or Snoop State

    For Intel® ° Xeon™ processor with 800 MHz system bus, the SLP# pin may only be asserted when all logical processors are in the Stop-Grant state. SLP# assertions while the processors are not in the Stop- Grant state are out of specification and may results in illegal operation.

  • Page 78: Demand-Based Switching (Dbs) With Enhanced Intel Speedstep® Technology

    Note: Not all Intel® Xeon™ processors are capable of supporting Demand-Based Switching (DBS) with Enhanced Intel SpeedStep® Technology. More details on which processor frequencies will support this feature will be provided in future releases of the Intel® Xeon™ Processor with 800 MHz System Bus Specification Update when available.

  • Page 79: Boxed Processor Specifications

    The Intel® Xeon™ processor with 800 MHz system bus will be offered as an Intel boxed processor. Intel will offer boxed the Intel® Xeon™ processor with 800 MHz system bus with three product configurations available for each processor frequency: 1U passive, 2U passive and 2U+ Active.

  • Page 80: 2U Passive Cek Heatsink

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 17. 2U Passive CEK Heatsink Figure 18. Active CEK Heatsink 3- and 4-Pin (representation only) Datasheet...

  • Page 81: Mechanical Specifications

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 19. Passive Intel® Xeon™ Processor with 800 MHz System Bus Thermal Solution (2U and larger) Heat sink screw Heat sink screw Heat sink Heat sink springs springs screws screws Heat sink...

  • Page 82: Top Side Board Keepout Zones (Part 1)

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 20. Top Side Board Keepout Zones (Part 1) Datasheet...

  • Page 83: Top Side Board Keepout Zones (Part 2)

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 21. Top Side Board Keepout Zones (Part 2) Datasheet...

  • Page 84: Bottom Side Board Keepout Zones

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 22. Bottom Side Board Keepout Zones Datasheet...

  • Page 85: Board Mounting Hole Keepout Zones

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 23. Board Mounting Hole Keepout Zones Datasheet...

  • Page 86: Volumetric Height Keep-Ins

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 24. Volumetric Height Keep-Ins Datasheet...

  • Page 87: 4-Pin Fan Cable Connector (For Active Cek Heatsink)

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 25. 4-Pin Fan Cable Connector (for active CEK heatsink) Datasheet...

  • Page 88: 4-Pin Baseboard Fan Header (For Active Cek Heatsink)

    Intel® Xeon™ Processor with 800 MHz System Bus Figure 26. 4-Pin Baseboard Fan Header (for active CEK heatsink) Datasheet...

  • Page 89: Boxed Processor Heatsink Weight

    8.3.1 Fan Power Supply (active CEK) Initially the boxed Intel® Xeon™ processor with 800 MHz system bus will be introduced with a 3- pin active fan heatsink solution. This heatsink solution requires a constant +12 V supplied to pin 2 and does not support variable voltage speed control or 3-pin pulse width modulation (PWM) control.

  • Page 90: Fan Cable Connector Pinout (3-Pin Active Cek Heatsink)

    A new 4-pin PWM/T-diode controlled active fan heatsink solution will replace the 3-pin thermistor controlled solution after initial boxed Intel® Xeon™ processor with 800 MHz system bus introduction. This new solution is being offered to help provide better control over pedestal chassis acoustics.

  • Page 91: Fan Cable Connector Pinout (4-Pin Active Cek Heatsink)

    Intel® Xeon™ Processor with 800 MHz System Bus Table 31. Fan Cable Connector Pinout (3-pin active CEK heatsink) Pin Number Signal Color Ground Black Power: (+12 V) Yellow Sense: 2 pulses per revolution Green Figure 28. Fan Cable Connector Pinout (4-pin active CEK heatsink) Table 32.

  • Page 92: Thermal Specifications

    Intel® Xeon™ Processor with 800 MHz System Bus Thermal Specifications This section describes the cooling requirements of the heatsink solution used by the boxed processor. 8.4.1 Boxed Processor Cooling Requirements As previously stated the boxed processor will be available in three product configurations. Each configuration will require unique design considerations.

  • Page 93: Boxed Processor Contents

    Intel® Xeon™ Processor with 800 MHz System Bus Boxed Processor Contents A direct chassis attach method must be used to avoid problems related to shock and vibration, due to the weight of the heatsink required to cool the processor. The board must not bend beyond specification in order to avoid damage.
  • Page 94 Intel® Xeon™ Processor with 800 MHz System Bus Datasheet...

  • Page 95: Debug Tools Specifications

    LAI is critical in providing the ability to probe and capture front side bus signals. There are two sets of considerations to keep in mind when designing a Intel® Xeon™ processor with 800 MHz system bus-based system that can make use of an LAI: mechanical and electrical.

  • Page 96: Mechanical Considerations

    Intel® Xeon™ Processor with 800 MHz System Bus 9.3.1 Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer.

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