Intel iAPX 86/88 User Manual page 5

Chapter 1
8086/8088 CPU
Table of Contents
1.1 Introduction................................................................. 1-1
1.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-1
1.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
1.2.2 Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12
1.3 Device Pin Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-42
1.3.1 Functional Description of All Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-43
1.3.2 Electrical Description of Pins .................................................. 1-43
1.3.3 Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-43
1.3.4 Minimum Mode System Overview/Description .............. , ..................... 1-44
1.3.5 Maximum Mode System Overview/Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-52
1.3.6 General Design Considerations ................................................ 1-64
1.4 Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-64
1.4.1 Multiplexed Address and Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-64
1.4.2 Bus Cycle Definition ........................................................ 1-65
1.4.3 Address and Data Bus Concepts ............................................... 1-66
1.4.4 Memory and
110
Peripherals Interface ........................................... 1-71
1.4.5 System DeSign Alternatives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-92
1.4.6 Multiprocessor/Coprocessor Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-97
1.4.7 Interpreting The 8086/8088 Bus Timing Diagrams ................................. 1-98
1.4.8 Wait State Insertion ......................................................... 1-107
1.4.9 8086/8088 Instruction Sequence ............................................ , .. 1-109
1.5 Bus Exchange Mechanisms .................................................... 1-110
1.5.1 Minimum Mode (HOLD/HLDA) ................................................ 1-110
1.5.2 Maximum Mode (RQ*/GT*) ................................................... 1-113
1.6 RESET .................................................................... 1-118
1.6.1 Reset Bus Conditioning ...................................................... 1-118
1.6.2 Multiple Processor Considerations ............................................. 1-119
1.7 Interrupts ................................................................... 1-120
1 .7.1 Classes of Interrupts ........................................................ 1-120
1.7.2 Divide Error-Type 0 ........................................................ 1-121
1.7.3 Single Step-Type 1 ........................................................ 1-121
1.7.4 Non-Maskable Interrupt-Type 2 ............................................... 1-121
1.7.5 One Byte Interrupt-Type 3 ................................................... 1-121
1.7.6 Interrupt on Overflow-Type 4 ........................................ ' ......... 1-121
1.7.7 User-Defined Software Interrupts .............................................. 1-122
1.7.8 User-Defined Hardware Interrupts .............................................. 1-122
1.7.9 Interrupt Acknowledge ....................................................... 1-122
1.8 Support Components ......................................................... 1-125
1.8.1 8284A Clock Generator and Driver ............................................. 1-125
1.8.2 8288 Bus Controller ......................................................... 1-130
1.8.3 8289 Bus Arbiter ........................................................... 1-133
1.8.4 8259A Programmable Interrupt Controller ....................................... 1-134
1.8.5 8237 A Programmable DMA Controller .......................................... 1-142
Chapter 2
80186/80188 CPU
2.1 Introduction-The High Integration Concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2 Component Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.1 Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
2.2.2 Software Overview .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-4
2.3 Device Pin Definitions ......................................................... 2-12
2.3.1 Functional Description of All Signals ............................................ 2-12
2.3.2 Electrical Description of Pins .................................................. 2-12
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