Intel iAPX 86/88 User Manual page 39

8086/8088 CPU
Table 1-13 Key to Flag Effects
IDENTIFIER EXPLANATION
(blank) not altered
0 cleared to 0
1 set to 1
X set or cleared according
to result
U
undefined-contains no
reliable value
R restored from previously-
saved value
The timings given for control transfer instructions include
any additional clocks required to reinitialize the instruc-
tion queue as well as the time required to fetch the target
instructions. For instructions executing on an 8086, four
clocks should be added for each instruction reference to a
word operand located at an odd memory address to reflect
any additional operand bus cycles required. Also, for in-
structions executing on an 8088, four clocks should be
added to each instruction reference to a 16-bit memory
operand. This includes stack operations. The required
number of data references is listed for each instruction in
Table 1-16 to aid in this calculation.
All of the instruction times given are of the form "n(m)" ,
where"n" is the number of clocks required for the 8086
to execute the given instruction, and "m" is the number of
clocks required by the 80186 for the same instruction.
The number of clocks required for the 8088 will be n for
8-bit operations and n
+
(4
*
transfers) for 16-bit opera-
tions. For the 80188, the number of clocks will be m for
8-bit operations and m
+
(4
*
transfers) for 16 bit
operations.
For instructions which repeat a specified number of times,
the values m and n each consist of two parts in the relation
"x
+
y/rep", where x is the initial number of clocks re-
quired
to
start the instruction, and y is the number of
clocks corresponding to the number of iterations speci-
fied. For 16-bit repeated instructions on the 8088 and
80188, when the expression "(4
*
transfers)" has to be
added to m or n, it should be added to the y part of the
expression before it is multiplied by the number of
repetitions.
Several additional factors can alter the actual execution
time from the figures shown in Table 1-16. The time pro-
vided assumes that the instruction has already been pre-
fetched and that it is waiting in the instruction queue. This
assumption is valid under most, but not all, operating con-
ditions. A series of fast executing (fewer than two clocks
per opcode byte) instructions can drain the queue and in-
crease execution time. Execution time is also slightly
Table 1-14 Key to Operand Types
IDENTIFIER
EXPLANATION
(no operands) No operands are written
register
reg 16
An 8- or 16-bit general register
A 16-bit general register
seg-reg A segment register
accumulator Register AX or AL
immediate A constant in the range
O-FFFFH
immed8
memory
mem8
A constant in the range O-FFH
An 8- or 16-bit memory
location(1)
An 8-bit memory location(1)
mem16 A 16-bit memory location(1)
source-table Name of 256-byte translate
table
source-string Name of string addressed by
register
SI
dest-string Name of string addressed by
register 01
OX Register OX
short-label A label within -128 to +127
bytes of the end of the instruc-
tion
near-label
far-label
near-proc
far-proc
memptr16
memptr32
regptr16
repeat
A label in current code
segment
A label in another code
segment
A procedure in current code
segment
A procedure in another code
segment
A word containing the offset of
the location in the current code
segment to which control is to
be transferred(1)
A doubleword containing the
offset and the segment base
address of the location in
another code segment to which
control is to be transferred(1)
A 16-bit general register
containing the offset of the
location in the current code
segment to which control is to
be transferred
A string instruction repeat
prefix
(1)Any addreSSing mode-direct, register in-
direct, based, indexed, or based
indexed-may be used
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