Effective Address Calculation Time; Instruction Set Reference Data - Intel iAPX 86/88 User Manual

8086/8088 CPU
Table 1·15 Effective Address Calculation Time
EA COMPONENTS
CLOCKS'
Displacement Only
6
Base or Index Only
(BX,BP,SI,DI)
5
Displacement
+
9
Base or Index (BX,BP,SI,DI)
Base
BP + 01, BX + SI
7
+
Index
BP+SI, BX+DI 8
Displacement
BP+DI+DISP
11
+
BX+SI+DISP
Base
+ BP+SI+DISP
12
Index
BX+ 01+ DISP
• Add 2 clocks for segment override
effected by the interaction of the EU and BIU when mem-
ory operands must be read or written. If the EU needs
access to memory, it may have to wait for up to one clock
if the BIU has already started an instruction fetch bus cy-
cle. (The EU can detect the need for a memory operand
and post a bus request far enough in advance of its need
for this operand to avoid waiting a full 4-clock bus cycle).
If the queue is full the EU does not have to wait because
the BIU is idle. (This assumes the BIU can obtain the bus
on demand and no other processors are competing for the
bus). .
With typical instruction mixes, the time actually required
to execute a sequence of instructions will be within
5 - 10% of the sum of the individual timings provided in
Table 1-16. Cases can be constructed, however, in which
execution time may be much higher than the sum of the
figures provided in the table. The execution time for a
given sequence of instructions is always repeatable, as-
smning . comparable external conditions (interrupts, co-
processor activity, etc.). Ifthe execution time for a given
series of instructions must be determined exactly, the in-
structions should be run on an execution vehicle such as
the iSBC 88/25 or 86/30 board.
MACHINE INSTRUCTION ENCODING AND
DECODING
Machine instruction encoding and decoding is primarily
the concern of the programmer. It is presented here for
the hardware designer since such encoding and decoding
Table 1·16 Instruction Set Reference Data
AAA
I
AAA (no operands)
ASCII adjust for addition
FIODITSZAPC
ags U U U X U X
Operands Clocks Transfers' Bytes Coding Example
(no operands)
8(8)
-
1
AAA
AAD
I
AAD (no operands)
ASCII adjust for division
FIODITSZAPC
ags U
XXUXU
Operands Clocks Transfers'
Bytes Coding Example
(no operands)
60(15)
-
2 ADD
AAM
I
AAM (no operands)
ASCII adjust for multiply
FI
0
0 ITS ZAP C
ags U
XXUXU
Operands Clocks Transfers' Bytes Coding Example
(no operands)
83(19)
-
2
AAM
AAS
I
AAS (no operands)
ASCII adjust for subtraction
FI
0 0 ITS ZAP C
ags U
UUXUX
Operands Clocks Transfers' Bytes
Coding Example
(no operands)
8(7)
-
1
AAS
• For the 8086 (80t 86) add. four clocks for each 16·M word transfer With an odd address. For the 8088 (80188) add four clocks for each 16·M wora
transfer.
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