Intel iAPX 86/88 User Manual page 13

TABLE OF CONTENTS
2-45 Source
&
Destination Synchronized DMA Request Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-56
2-46 Timer Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
2-47 80186 Timer Out Signal ........................................................... 2-59
2-48 Example Timer Interface Code ..................................................... 2-60
2-49 80186 Real Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-64
2-50 80186 Baud Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-64
2-51 80186 Event Counter ............................................................. 2-65
2-52 Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-65
2-53 iRMXTM 86 Interrupt Controller Interconnection ........................................ 2-66
2-54 80186 Interrupt Controller Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
2-55 INTO/INT1 Control Register Formats ................................................. 2-66
2-56 INT2/INT3 Control Register Format .................................................. 2-67
2-57 80186 Interrupt Sequencing ....................................................... 2-67
2-58 Interrupt Controller Control Register ................................................. 2-68
2-59 80186 Non-Cascaded Interrupt Connection ........................................... 2-69
2-60 Cascade and Special Fully Nested Mode Interface ...................................... 2-69
2-61 80186/8258A Interrupt Cascading ................................................... 2-70
2-62 Example Interrupt Controller Interface Code ........................................... 2-71
2-63 80186 iRMXTM 86 Mode Interface ................................................... 2-72
2-64 80186/80130 iRMXTM 86 Mode Interface ............................................. 2-72
2-65 80186 iRMXTM 86 Mode Interrupt Acknowledge Timing .................................. 2-74
2-66 80186 Cascaded Interrupt Acknowledge Timing ........................................ 2-75
2-67 80186 Memory Areas and Chip Selects .............................................. 2-75
2-68 80186 Chip Select Control Registers ................................................. 2-76
2-69 UMCS Register ................................................................. 2-77
2-70 LMCS Register. ................................................................. 2-77
2-71 MPCS Register ................................................................. 2-77
2-72 MMCS Register ................................................................. 2-78
2-73 Clock In/Clock Out Timing ......................................................... 2-79
2-74 80186 Clock Generator Block Diagram ............................................... 2-79
2-75 Recommended iAPX 186 Crystal Configuration ........................................ 2-80
2-76 80186 Crystal Connection ......................................................... 2-80
2-77 80186 Clock Generator Reset ...................................................... 2-81
2-78 Coming out of Reset ............................................................. 2-81
3-1 Submit file Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-2
3-2 8087 Numeric Data Processor Pin Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-3
3-3 Typical iAPX 86/2X Family System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-4
3-4 Typical iAPX 186/2X Family System Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
3-5 Test for the Existence of an 8087. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
3-6 iSBC 337 MULTIMODULE Mounting Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
3-7 8087 Numeric Processor Extension Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-6
3-8 Non-Memory Reference Escape Instruction Form ...................................... 3-7
3-9 Memory Reference Escape Instruction Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-8
3-10 ESCAPE Instructions Not Used By the 8087 NPX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-8
3-11 8087 NPX-8086/88 CPU System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
3-12 8087 NPX-80186/188 CPU System Configuration ..................................... 3-12
3-13 Synchronizing Execution With WAIT ................................................. 3-15
3-14 Three Processor System Bus Signal Connections ...................................... 3-17
3-15 iAPX 88/21 System Configuration ................................................... 3-18
3-16 iAPX 86/22 System . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . 3-20
3-17 SMALLBLOCK-NP)LSAVE ..................................................... 3-21
3-18 SMALLBLOCK-NP)LRESTORE ................................................. 3-21
3-19 NP)LCLEAN Code Example ...................................................... 3-22
3-20 Inhibit/Enable 8087 Interrupts ...................................................... 3-23
4-1 8089 Simplified Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-2
4-2 Channel Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
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