Intel iAPX 86/88 User Manual page 10

TABLE OF CONTENTS
1-26 String Operand Addressing .......................... ; ......... , ..... : ; ........... , 1-21
1-27 110 Port Addressing ................................................. " ........... 1-21
1-28 Typical 8086/88 Machine Instruction Format. ...................... , ................... 1-41
1-29 Machine Instruction Encoding Matrix ................................................ 1-44
1-30 8086/8088 DIP Pin Assignments .................................................... 1-65
1-31 Minimum Mode Waveforms ........................................................ 1-72
1-32 Maximum Mode Waveforms ....................................................... 1-74
1-33 Elementary Maximum Mode System ................................................. 1-76
1-34 8086/88 Minimum Mode System ................................................ : ... 1-77
1-35 8086/88 Maximum Mode System ................................................... 1-77
1-36 8086/88 Queue Tracking Circuit .................................................... 1-78
1-37 8086/88 Lock Activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-78
1-38 Decoding Memory and 110 RD" and WR" Commands ................................... 1-79
1-39 Linear Select for 110 . ............................................................. 1-79
1-40 Basic 8086/88 Bus Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-80
1-41 8086 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-80
1-42 Memory Even and Odd Data Byte Transfers .......................................... , 1-81
1-43 Memory Even and Odd Data Word Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-82
1-44 8086/8088 Memory Organization ............................. , ..................... 1-82
1-45 Reserved Memory Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-82
1-46 8086/8088 Memory Array ......................................................... 1-83
1-47 EPROMIROM Bus Interface ....................................................... 1-83
1-48 Chip Select Generation for Devices Without Output Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-83
1-49 Chip Selection for Devices With Output Enables ....................................... 1-84
1-50 Sample Compatibility Analysis Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-84
1-51 5 MHz 8086 System USing an 8202 Dynamic RAM Controller ............................. 1-85
1-52 8202 Timing Information ............................................. , ............ 1-86
1-53 2118 Family Timing .............................................................. 1-87
1-54
110 Device Chip Select Techniques .................................................. 1-88
1-55 16-bit to 8-bit Bus Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-88
1-56 Bipolar PROM Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-88
1-57 16-bit I/O Decode ................................................................ 1-88
1-58 8086 System Configurations ...................................................... , 1-90
1-59 Device Assignment ..................................... ; . . . . . . . . . . . . . . . . . . . . . . .. 1-91
1-60
110 Input Request Code Example ................................ , ................. , 1-92
1-61
Block Transfer to 16-bit 110 Using 8086/88 String Primitives ............................... 1-92
1-62 Block Transfer to 8-bit 110 USing 8086/88 String Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. 1-92
1-63 Code For Block Transfers .......................................................... 1-93
1-64 Multiplexed Data Bus ............................................................. 1-93
1-65 Buffered Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-93
1-66 Devices With Output Enable on the Multiplexed Bus .................................... 1-93
1-67 Relationship of ALE to READ ...................................................... 1-94
1-68 Devices Without Output Enable on the Multiplexed Bus .................................. 1-94
1-69 Access Time: CS Gated with AO"twR" .............................................. 1-94
1-70 CE TO WR" Setup and Hold ...................................................... , 1-94
1-71 Bus Transceiver Control. .......................................................... 1-95
1-72 Devices With Output Enable on the System Bus ....................................... 1-95
1-73 CS"/Bus Driving Device Timing .................................................... 1-95
1-74 De-multiplexing Address and Data From the Processor Bus .............................. 1-96
1-75 Multiplexed Bus With Local Address Oemultiplexing ................................... , 1-96
1-76 Fully Buffered System ...................................................•......... 1-97
1-77 ContrOlling System Transceivers with DEN and OT/R" ................................... 1-97
1-78 Buffering Devices with OE"/RO" ......................................... " ..... " .. 1-97
1-79 Buffering Devices Without OE"/RO" and With Common or Separate Input/Output. ............ 1-97
1-80 Buffering Devices Without OE"/RO" and With Common or Separate Input/Output ............. 1-97
1-81 Buffering Devices Without OE"/RO" and With Separate Input/Output. ...................... 1-98
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