Intel iAPX 86/88 User Manual page 21

8086/8088 CPU
GENERAL
REGISTERS
AH AL
BL
CH
OH OL
BP
01
51
CS
os
ss
ES
INTERNAL
COMMUNICATIONS
REGISTERS
DATA SUS
(6 BITS)
sus
INTERFACE UNIT
(BIU)
BUS
CONTROL
LOGIC
8088
BUS
Figure 1-4 8088 Simplified Functional Block Diagram
first and second generation microprocessors. The P & I
registers (except for BP) are also used implicitly in some
instructions (see Table I-I).
SEGMENT REGISTERS
The 8086 and 8088 memory space (up to one megabyte) is
divided into logical segments of up to 64k bytes each. The
CPU has direct access to four segments at a time. The
base addresses (starting locations) of these memory seg-
ments are contained in the segment registers (see Figure
1-7). The CS register points to the current code segment.
Instructions are fetched from the CS segment. The SS
register points to the current stack segment. Stack opera-
tions are performed on locations in the SS segment. The
DS register points to the current data segment. The DS
register generally contains program variables. The ES
register points to the current extra segment, which also is
typically used for data storage.
The segment registers are accessable to programs and can
be manipulated with several instructions. Good program-
ming practice and consideration of compatibility with fu-
ture Intel hardware and software products dictate that the
segment registers be used in a disciplined fashion.
1-5
INSTRUCTION POINTER
The 16-bit instruction pointer (IP) is similar to the pro-
gram counter (PC) in the 8080/8085 CPUs. The instruc-
tion pointer is updated by the BIU so that it contains the
offset (distance in bytes) of the next instruction from the
beginning of the current code segment; i.e., IP points to
the next instruction. During normal execution, IP con-
tains the offset of the next instruction to be fetched by the
BIU. Whenever IP is saved on the stack, however, it is
first automatically adjusted to point to the next instruction
to be executed. Programs do not have direct access to the
instruction pointer, but instructions cause it to change and
to be saved on and restored from the stack.
FLAGS
The 8086 and 8088 have six I-bit status flags (see Figure
1-8) that the EU posts to reflect certain properties of the
result of an arithmetic or logic operation. A group of in-
structions is available that allows a program to alter its
execution depending on the state of these flags, i.e., on
the result of a prior operation. Different instructions af-
fect the status flags differently; in general, however, the
flags reflect the following conditions:
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