Intel iAPX 86/88 User Manual page 59

8086/8088
CPU
Table 1-20 Register/Memory Field Encoding
MOD=11 EFFECTIVE ADDRESS CALCULATION
RIM W=O W=1 RIM MOD=OO MOD=01
MOD=1~
000 AL AX 000 (BX)+(SI) (BX)+(SI)+08 (BX)+(SI)+016
001
CL CX 001
(BX)+(OI)
(BX)+(0I)+08
(BX)+(0I)+016
010 OL OX 010
(BP)+(SI)
(BP)+(SI)+08 (BP)+(SI)+016
011 BL BX 011
(BP)+(OI)
(BP) + (01) + 08 (BP) + (01) + 016
100 AH SP 100
(SI)
(SI)+08 (SI)+016
101 CH BP 101 (01)
(01)+08
(01)+ 016
110 OH SI 110 OIRECT AOORESS (BP)+08 (BP)+016
111 BH 01 111 (BX)
1.3.1 Functional Description of All Signals
Figure 1-30 shows the 8086/8088 DIP pin assignments
and Table 1-24 provides a complete functional description
of each device pin signal and correlates the description to
the pin number and associated signal symbol.
1.3.2 Electrical Description of Pins
The absolute maximum ratings for the 8086/8088 device
are as follows.
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to
GND
OOC to 70°C
-65°C to
+ 150°C
-1.0to +7V
Power Dissipation 2. S Watt
Stresses above those listed above may cause permanent
damage to the device. These values present stress ratings
only and functional operation of the device at these or
any other conditions above those indicated in the opera-
tional sections of the device specifications is not implied.
Exposure to absolute maximum conditions for extended
periods of time may affect the device reliability.
Table 1-25 presents the D. C. voltage characteristics of the
8086/8088 CPU's. Table 1-26 lists the A.C. characteris-
tics timing requirements and timing responses for mini-
mum complexity systems, and Table 1-27 lists the A.C.
characteristics timing requirements and timing responses
for maximum complexity systems (using 8288 bus
controller). Figure 1-31 and Figure 1-32 presents wave-
forms for the minimum mode and maximum mode
operation related to the preceding A. C. characteristics
tables.
1-43
(BX)+08
(BX)+016
1.3.3 OPERATING MODES
One of the unique features the 8086 and 8088 CPU's al-
low the user is the ability to select between two functional
definitions of a subset of the 8086/8088 outputs. This en-
ables the user to tailor the intended CPU system environ-
ment. This "system tailoring" is accomplished by
strapping the CPU's MN/MX* (minimum/maximum) in-
put pin. Table 1-28 defines the 8086 and 8088 pin assign-
ments for both the minimum and maximum modes of
operation.
In the minimum mode, the CPU's support small systems
by strapping the MN/MX* pin to + SY. In this mode of
operation, the 8086/8088 CPU generates all bus control
signals (DT/R*, DEN*, ALE and either M/IO* or
IO/M*) and the command output signals (RD*, WR* or
INTA *). The CPU also provides a mechanism for re-
questing bus access (HOLDIHLDA) that is
compa~ible
with bus master type controllers (e.g., the Intel 8237A
DMA Controller).
When a bus master requires bus access in the minimum
mode, it activates the HOLD input to the CPU through its
request logic. In response to the "hold" request, The
CPU activates HLDA as an acknowledgement to the bus
master, requesting the bus, and simultaneously floats the
system bus and control lines. Since a bus request is asyn-
chronous, the CPU samples the HOLD input on the posi-
tive transition of each CLK signal and activates HLDA at
the end of either the current bus cycle (if a bus cycle is in
progress) or idle clock period. The CPU maintains the
hold state until the bus master inactivates the HOLD in-
put. At that time the CPU regains control of the system
bus. Note that during a "hold" state, the CPU continues
to execute instructions until a bus cycle is required.
In the minimum mode, the VO-memory control line for
the 8088 CPU is the reverse of the corresponding control
line for the 8086 CPU (M/IO* on the 8086 and IO/M* on
the 8088). Since the 8088 CPU is an 8-bit device, this
conditioning provides compatibility with existing
MCS® -85 systems specific MCS-85 family devices (e.g.,
the Intel 8155/56).
210912-001