Intel iAPX 86/88 User Manual page 57

8086/8088 CPU
Table 1-16 Instruction Set Reference Data (continued)
XOR
I
XOR destination, source
Logical exclusive or
FI 0 D I T 5 ZAP C
ags
0
XXUXO
Operands Clocks Transfers· Bytes Coding Example
register, register 3(3)
-
2 XORCX, BX
register, memory 9(10)+ EA 1 2-4 XOR CL, MA5LBYTE
memory, register 16(10)+EA 2 2-4 XOR ALPHA [51], DX
accumulator, immediate 4(3-4)
-
2-3 XOR AL, 010000108
register, immediate 4(4)
-
3-4
XOR 51, 00C2H
memory, immediate 17(16)+EA 2 3-6 XOR RETURN_CODE, OD2H
• For the 8086 (80186) add four clocks for each 16-bit word transfer with an odd address. For the 8088 (80188) add four clocks for each 1S-bit word
transfer.
directly affects bus activity. As an example of the encod-
ing and decoding process, consider writing a MOV in-
struction in ASM-86 in the form:
MOV destination , source
This will cause the assembler to generate I of 28 possible
forms of the MOV machine instruction. A programmer
rarely needs to know the details of machine instruction
formats or encoding. An exception may occur during de-
bugging when it may be necessary to monitor instructions
fetched on the bus, read unformatted memory dumps, etc.
This section provides the information necessary to trans-
late or decode an 8086 or 8088 machine instruction.
To pack instructions into memory as densely as possible,
the 8086 and 8088 CPUs utilize an efficient coding tech-
nique. Machine instructions vary from one to six bytes in
length. One-byte instructions, which generally operate on
single registers or flags, are simple to identify; the keys to
decoding longer instructions are in the first two bytes.
The format of these bytes can vary, but most instructions
follow the format shown in Figure 1-28.
The first six bits of a multibyte instruction generally con-
tain an opcode that identifies the basic instruction type:
ADD, XOR, etc. The following bit, called the 0 field,
generally specifies the "direction" of the operation: 1 =
the REG field in the second byte identifies the destination
operand, 0 = the REG field identifies the source oper-
and. The W field distinguishes between byte and word
operations: 0
=
byte, 1
=
word.
One of three additional single-bit fields, S, V or Z, ap-
pears in some instruction formats (refer to Table 1-17). S,
in conjunction with W, indicates the sign extension of im-
mediate fields in arithmetic instructions. V distinguishes
between single-and variable-bit shifts and rotates. Z is a
compare bit with the zero flag in conditional repeat and
loop instructions.
The second byte of the instruction usually identifies the
instruction's operands. The MOD (mode) field indicates
whether one of the operands is in memory or whether
both operands are registers (refer to Table 1-18). The
REG (register) field identifies a register that is one of the
instruction operands (refer to Table 1-19). In a number of
instructions, particularly the immediate-to-memory vari-
ety, REG is used as an extension of the opcode to identify
the type of operation. The encoding of the R/M
(register/memory) field (refer to Table 1-20) depends on
how the mode field is set.
If
MOD = 11
BYTE 1 BYTE 2
BYTE 3 BYTE 4 BYTE 5 BYTE 6
II II
OPCODE
I II II
Dlw MOD REG R/M
~
------~-----r-----~------l
I I I I
LOW DISP/DATA
I
HIGH DISP/DATA
I
LOW DATA
I
HIGH DATA
I
I I I I
-----------~------~-----~
REGISTER OPERAND/REGISTERS TO USE IN EA CALCULATION
REGISTER OPERAND/EXTENSION OF OPCODE
REGISTER MODE/MEMORY MODE WITH DISPLACEMENT LENGTH
WORD/BYTE OPERATION
DIRECTION IS TO REGISTER/DIRECTION IS FROM REGISTER
OPERATION (INSTRUCTION) CODE
Figure 1-28 Typical 8086/88 Machine Instruction Format
1-41
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