Interrupts; Segment Registers; Status Flags - Intel iAPX 86/88 User Manual

8086/8088 CPU
DATA {
GROUP
POINTER {
AND
INDEX
GROUP
H
15
I
I
8 7
I - -
AH -
~
-Ai: - -
BX
I-
- B H -
-r - IiL. - -
I----~----
CH CL
1--6H-~-DL--
15 0
SP
BP
SI
01
ACCUMULATOR
BASE
COUNT
DATA
STACK
POINTER
BASE
POINTER
SOURCE
NDEX I
DESTINATION
NDEX I
Figure 1-6 General Registers
15
CS
CODE
SEGMENT
OS
DATA
SEGMENT
SS
STACK
SEGMENT
ES
EXTRA
SEGMENT
Figure 1-7 Segment Registers
Table 1-1 Implicit Use of General Registers
REGISTER
OPERATIONS
AX
Word Multiply, Word Divide,
Word 1/0
AL Byte Multiply, Byte Divide, Byte
1/0, Translate, Decimal Arithmetic
AH Byte Multiply, Byte Divide
BX Translate
CX
String Operations, Loops
CL Variable Shift and Rotate
OX
Word Multiply, Word Divide,
Indirect 1/0
SP
Stack Operations
SI
String Operations
01
String Operations
1-7
m
F
B~CARRY
~PARITY
AUXILIARY CARRY
' - - - - - - - ZERO
' - - - - - - - - - SIGN
' - - - - - - - - - - O V E R F L O W
' - - - - - - - - - - - I N T E R R U P T - E N A B L E
' - - - - - - - - - - - - - - O I R E C T l O N
' - - - - - - - - - - - - - - - T R A P
Figure 1-8 Status Flags
1. Setting DF (the direction flag) causes string instruc-
tions to auto-decrement; that is, to process strings
from the high address to the low address, or from
"right to left." Clearing DF causes string instructions
to auto-increment, or process strings from "left to
right."
2. Setting IF (the interrupt-enable flag) allows the CPU
to recognize external (maskable) interrupt requests.
Clearing IF disables these interrupts. IF has no affect
on either non- maskable external or internally gener-
ated interrupts.
3. Setting TF (the trap flag) puts the processor into
single-step mode for debugging. In this mode, the
CPU automatically generates an internal interrupt af-
ter each instruction, allowing a program to be in-
spected as it executes instruction by instruction.
MODE SELECTION
Each of the processors has a strap pin (MN/MX*) that
defines the function of eight CPU pins in the 8086 and
nine pins in the 8088. Connecting MN/MX* to
+
5V
places the CPU in minimum mode. This configuration is
designed for small systems (roughly one or two boards)
and the CPU provides bus control signals needed by
memory and peripherals. When MN/MX* is strapped to
ground, the CPU is configured in maximum mode. In this
configuration the CPU encodes control signals on three
lines. An 8288 Bus Controller is added to decode the sig-
nals for the rest of the system. The CPU uses the remain-
ing free lines for a new set of signals designed to help
coordinate the activities of other processors in the system.
SEGMENTATION
Programs for the 8086 and 8088 "view" the memory
space ( one megabyte) as a group of segments that are de-
fined by application. A segment is a logical unit of mem-
ory that may be up to 64k bytes long. Each segment is
made up of contiguous memory locations and is an inde-
pendent, separately-addressable unit. Every segment is
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