Program Transfer Instructions - Intel iAPX 86/88 User Manual

8086/8088 CPU
If a repeat prefix has been coded, then register CX (count
register) is decremented by 1 after each repetition of the
string instruction. CX must
be
initialized to the number of
repetitions desired before the string instruction is exe-
cuted. If CX is 0, the string instruction is not executed,
and control goes to the following instruction.
Program Transfer Instructions
The sequence in which instructions are executed in the
8086/8088 is determined by the content of the code seg-
ment register (CS) and the instruction pointer (lP). The
CS register contains the base address of the current code
segment, the 64k portion of memory from which instruc-
tions are currently being fetched. The IP points to the
memory location from which the next instruction is to be
fetched. In most operating conditions, the next instruction
to be executed will have already been fetched and is wait-
ing in the CPU instruction queue. The program transfer
instructions operate on the instruction pointer and on the
CS register; changing the content of these causes normal
sequential operation to be altered. When a program trans-
fer occurs, the queue no longer contains the correct in-
struction. When the BIU obtains the next instruction from
memory using the new IP and CS values, it passes the
instruction directly to the EU and then begins refilling the
queue from the new location.
Four groups of program transfers are available with the
8086/8088 CPU's. See Table 1-9. These are unconditional
transfers, conditional transfers, iteration control instruc-
tions, and interrupt-related instructions.
a. Unconditional Transfers
The unconditional transfer instructions may transfer con-
trol to a target instruction within the current code segment
(intrasegment transfer) or to a different code segment (in-
tersegment transfer). The ASM-86 Assembler terms an
intrasegment transfer SHORT or NEAR and an interseg-
ment transfer FAR. The transfer is made unconditionally
any time the instruction is executed.
b. Conditional Transfers
The conditional transfer instructions are jumps that may
or may not transfer control depending on the state of the
CPU flags at the time the instruction is executed. These
18 instructions (see Thble 1-10) each test a different com-
bination of flags for a condition. If the condition is "true"
then control is transferred to the target specified in the
instruction. If the condition is "false" then control passes
to the instruction that follows the conditional jump. All
conditional jumps are SHORT, that is, the target must be
in the current code segment and within -128 to
+
127
bytes of the first byte of the next instruction (IMP OOH
jumps to the first byte of the next instruction). Since
Table 1·9 Program Transfer Instructions
UNCONDITIONAL TRANSFERS
CALL
Call procedure
RET Return. from procedure
JMP Jump
CONDITIONAL TRANSFERS
JA/JNBE Jump if above/not below
nor equal
JAE/JNB Jump if above or
equal/not below
JB/JNAE Jump if below/not above
nor equal
JBE/JNA Jump if below or
equal/ not above
JC Jump if carry
JE/JZ Jump if equal/zero
JG/JNLE Jump if greater/not less
nor equal
JGE/JNL Jump if greater or
equal/not less
JLlJNGE Jump if less/not greater
nor equal
JLE/JNG Jump if less or equal/not
greater
JNC Jump if not carry
JNE/JNZ
Jump if not equal/not
zero
JNO Jump if not overflow
JNP/JPO Jump if not parity/parity
odd
JNS Jump if not sign
JO
Jump if overflow
JP/JPE Jump if parity / parity
even
JS Jump if sign
ITERATION CONTROLS
LOOP Loop
LOOPE/LOOPZ Loop if equal/zero
LOOPNE/LOOPNZ Loop if not equal/not
zero
JCXZ Jump if register CX
=
0
INTERRUPTS
INT
Interrupt
INTO Interrupt if overflow
IRET
Interrupt return
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