Intel iAPX 86/88 User Manual page 12

TABLE OF CONTENTS
1-138 Cascaded 8259A's22 Interrupt Levels ....................................... , ....... 1-141
1-139 Cascade-Buffered Mode Example ................................................... 1-143
1-140 8237A DMA Controller Block Diagram ............................................... 1-143
1-141 Cascaded 8237As ............................................................... 1-145
1-142 Memory-To-Memory Transfer Timing ................................................. 1-146
1-143 Command Register .............................................................. 1-147
1-144 Software Command Codes ........................................................ 1-147
1-145 Mode Register .................................................................. 1-147
1-146 Request Register ................................................................ 1-147
1-147 Mask Bits ...................................................................... 1-148
1-148 Mask Register .................................................................. 1-148
1-149 Status Register ................................................................. 1-148
2-1 80186/80188 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
2-2 ENTER Instruction Stack Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-7
2-3 Flag Store Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
2-4 80186/80188 DIP Pin Assignments .................................................. 2-19
2-5 Major Cycle Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
2-6 Generating Queue Status Information ................................................ 2-28
2-7 80186 and 8086 Queue Status Generation ............................................ 2-29
2-8 Example 80186 Buffered/Unbuffered Data Bus ........................................ 2"30
2-9 Read Cycle Timing .............................................................. 2-30
2-10
Generating 1/0 and Memory Read Signals ............................................ 2-31
2-11 Write Cycle Timing ............................................................... 2-31
2-12 Synthesizing Delayed Write from the 80186 ........................................... 2-32
2-13 Active-Inactive Status Transitions ................................................... 2-32
2-14 80186/8288 Bus Controller Interconnection ........................................... 2-32
2-15 Circuit Holding LOCK' Active Until Ready Is Returned .................................. 2-33
2-16 80186/8288/8289 Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2-17 Physical Memory BytelWord Addressing .............................................. 2-35
2-18 80186/External Chip SelectlDevice Chip Select Generation .............................. 2-35
2-19 Example 2764/80186 Interface ..................................................... 2-35
2-20 Example 2186/80186 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-37
2-21 Example 8203/DRAM/80186 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 2-38
2-22 8203/2164A-15 Access Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-39
2-23 8208 Dynamic RAM Controller Interfaces ............................................. 2-40
2-24 8208 Processor Address Interfaces .................................................. 2-41
2-25 8208 Differentiated Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-42
2-26 Single T-State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-42
2-27 Example 80186 Bus Cycle ......................................................... 2-43
2-28 80186 Address Generation Timing .................................................. 2-43
2-29 Demultiplexing the 80186 Address Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-44
2-30 Valid/lnvalid ARDY Transitions ...................................................... 2-45
2-31 Asynchronous Ready Circuits for the 80186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46
2-32 Valid SRDY Transitions on the 80186 ............. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-46
2-33 Valid & Invalid Latch Input Transitions & Responses ..................................... 2-47
2-34 Signal FloatlHLDA Timing ......................................................... 2-47
2-35 80186 Idle Bus HOLD/HLDA Timing ............................................... " 2-48
2
c
36 HOLD/HLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-49
2-37 End of HOLD Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-49
2-38 80186 CPUlDMA Channel Internal Model ............................................. 2-51
2-39 80186 DMA Register Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
2-40 DMA Control Register .............. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-52
2-41 Example DMA Transfer Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. 2-53
2-42 DMA Request Timing ............................................................. 2-55
2-43 DMA Request Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-55
2-44 DMA Acknowledge Synthesis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-55
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