Intel iAPX 86/88 User Manual page 18

8086/8088 CPU
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Figure 1·1 Small8088·8ased System
stack. The hardware addressing modes provide efficient,
straightforward implementations of based variables, ar-
rays, arrays of structures and other high-level language
data constructs. A powerful set of memory-to-memory
string operations is available for efficient character data
manipulation. Finally, routines with critical performance
requirements that cannot be met with PLlM-86 may be
written in ASM-86 (the 8086/8088 assembly language)
and linked with PLlM-86 code.
Although the 8086 and 8088 Microprocessors are totally
new designs, they make the most of user's existing invest-
ments in systems designed around the 8080/8085 micro-
processors. Many of the standard Intel memory,
peripheral control and communication chips are compati-
ble with the 8086 and the 8088. Software is developed in
the familiar Intellec Microcomputer Development System
environment, and most existing programs, whether writ-
ten in ASM-80 or PLlM-80, can be directly converted to
run on the 8086 and 8088.
1.2.1 Architectural Overview
Both the 8086 and 8088 microprocessors incorporate two
separate processing units (see Figures 1-3 and 1-4). These
are the Execution Unit (EU) and the Bus Interface Unit
(BID). Both microprocessors contain identical EU's. In
1-2
the 8086 the BID incorporates a 16-bit data bus and a
6-byte instruction queue. In the 8088 the BID incorpo-
rates an 8-bit data bus and a 4-byte instruction queue.
The EU executes instructions and the BIU fetches instruc-
tions, reads operands and writes results. The two units can
operate independently of one another and are able, under
most circumstances, to extensively overlap instruction
fetch with execution. The result is that, in most cases, the
time normally required to fetch instructions "disappears"
because the EU executes instructions that have already
been fetched by the BID. Figure 1-5 illustrates this over-
lap and compares it with traditional microprocessor oper-
ation. In the example, overlapping reduces the elapsed
time required to execute three instructions, and allows two
additional instructions to be prefetched as well.
In the 8086 CPU, when two or more bytes of the 6-byte
instruction queue are empty and the EU does not require
the BIU to perform a bus cycle, the BIU executes instruc-
tion fetch cycles to refill the queue. In the 8088 CPU,
when one byte of the 4-byte instruction queue is err-pty.
the BID executes an instruction fetCh cycle. Note that
since the 8086 CPU has a 16-bit data bus, it can access
two instruction object code bytes in a single bus cycle.
Since the 8088 CPU has an 8-bit data bus, it accesses one
instruction object code byte per bus cycle. If the EU
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