Interpretation Of Conditional Transfers; Processor Control Instructions - Intel iAPX 86/88 User Manual

8086/8088 CPU
Table 1·10 Interpretation of Conditional Transfers
MNEMONIC CONDITION TESTED "JUMP IF .....
JA/JNBE (CF
OR
ZF)=O above/not below nor equal
JAE/JNB CF=O above or equal/not below
JB/JNAE CF=1 below Inot above nor equal
JBE/JNA (CF
OR
ZF)=1 below or equal I not above
JC
CF=1
carry
JE/JZ
ZF=1
equal/zero
JG/JNLE ((SF
XOR
OF)
OR
ZF)=O greater I not less nor equal
JGE/JNL (SF
XOR
OF)=O greater or equal/not less
JLIJNGE
(SF
XOR
OF)=1
less/not greater nor equal
JLE/JNG ((SF
XOR
OF)
OR
ZF)=1 less or equal I not greater
JNC CF=O not carry
JNE/JNZ ZF=O not equal I not zero
JNO OF=O not overflow
JNPIJPO PF=O not parity I parity odd
JNS SF=O not sign
JO
OF=1
overflow
JP/JPE PF=1 parity I parity equal
JS
SF=1
sign
Note: "above" and "below" refer to the relationship of two unsigned values;
"greater" and "less" refer to the relationship of two signed values.
jumps are made by adding the relative displacement of the
target to the instruction pointer, all conditional jumps are
self-relative and are appropriate for position-independent
routines.
c. Iteration Control
The iteration control instructions can be used to regulate
the repetition of software loops. These instructions use the
CX register as a counter. Like the conditional transfers,
the iteration control instructions are self-relative and may
only transfer to targets that are within
-128
to
+
127
bytes of themselves, i.e., they are SHORT transfers.
d. Interrupt Instructions
The interrupt instructions allow interrupt service routines
to be activated by programs as well as by external hard-
ware devices. The effect of software interrupts is similar
to hardware-initiated interrupts. However, the processor
does not execute an interrupt acknowledge bus cycle if the
interrupt originates in software or with an NMI.
Processor Control Instructions
The processor control instructions (see Table 1-11) allow
programs to control various CPU functions. One group of
instructions updates flags, and another group is used pri-
marily for synchronizing the 8086 or 8088 to external
events. A final instruction causes the CPU to do nothing.
Except for the flag operations, none of the processor con-
trol instructions affect the flags.
1-17
OPERAND ADDRESSING MODES
The 8086 and 8088 access instruction operands in many
different ways. Operands may be contained in registers,
within the instruction itself, in memory, or at I/O ports.
Also, the addresses of memory and I/O port operands can
be calculated in several different ways. These addressing
Table 1·11 Processor Control Instructions
FLAG OPERATIONS
STC Set carry flag
CLC Clear carry flag
CMC
Complement carry flag
STO Set direction flag
CLO
Clear direction flag
STI Set interrupt enable flag
CLI Clear interrupt enable flag
EXTERNAL SYNCHRONIZATION
HLT Halt until interrupt or reset
WAIT Wait for TEST pin active
ESC Escape to external processor
LOCK Lock bus during next
instruction
NO OPERATION
NOP No operation
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