General Registers - Intel iAPX 86/88 User Manual

8086/8088
CPU
GENERAL
REGISTERS
AH Al
Bl
CH Cl
SP
BP
SI
ALU DATA BUS
(1& BITSI
EXECUTION UNIT
(EUI
DATA BUS
CS
OS
INTERNAL
COMMUNICATIONS
REGISTERS
(16 BITS)
BUS INTERFACE UNIT
(Btu)
BUS
CONTROL
LOGIC
808&
BUS
Figure 1-3 8086 Simplified Functional Block Diagram
six instruction bytes. These queue sizes allow the BIU to
keep the EU supplied with pre fetched instructions under
most conditions without monopolizing the system bus.
The 8088 BIU fetches another instruction byte whenever
one byte in its queue is empty and there is no active re-
quest for bus access from the EU. The 8086 BIU operates
similarly except that it does not initiate a fetch until there
are two empty bytes in its queue. The 8086 BIU normally
obtains two instruction bytes per fetch. If a program
transfer forces fetching from an odd address, the 8086
automatically reads one byte from the odd address and
then resumes fetching two-byte words from the subse-
quent even addresses.
In most circumstances the queues contain at least one byte
of the instruction stream and the EU does not have to wait
for instructions to be fetched. The instructions in the
queue are those stored in memory locations immediately
adjacent to and higher than the instruction currently being
executed. That is, they are the next logical instructions so
long as execution proceeds serially. If the EU executes an
instruction that transfers control to another location, the
BIU resets the queue, fetches the instruction from the new
address, passes it immediately to the EU, and then begins
refilling the queue from the new location. In addition, the
BIU suspends instruction fetching whenever the EU
1-4
requests a memory or 110 read or write (except that a
fetch already in progress is completed before executing
the EU's bus request).
GENERAL REGISTERS
Both CPU's have the same complement of eight 16-bit
general registers (see Figure 1-6). The general registers
are subdivided into two sets of four registers each. These
are the data registers (sometimes called the H & L group
for "high" and "low"), and the pointer and index regis-
ters (sometimes called the P & I group).
The data registers are unique in that their upper (high) and
lower halves are separately addressable. This means that
each data register can be used interchangeably as a 16-bit
register, or as a two 8-bit registers. The other CPU regis-
ters are always accessed as 16-bit only. The data registers
can be· used without constraint in most arithmetic and
logic operations. In addition, some instructions use cere
tain registers implicitly (see Table 1-1), therefore allow-
ing compact yet powerful encoding.
The pointer and index registers can also be used in most
arithmetic and logic operations. All eight general regis-
ters fit the definition of an "accumulator" as defined in
210912-001