Intel iAPX 86/88 User Manual page 19

8086/8088 CPU
Figure 1·2 8086/8088/8089 Multiprocessing System
issues a request for bus access while the BIU is in the
process of an instruction fetch bus cycle, the BIU comple-
tes the cycle before honoring the EU's request.
EXECUTION UNIT
The execution units (EU's) of the 8086 and 8088 are iden-
tical (see Figures 1-3 and 1-4). The EU is responsible for
the execution of all instructions, for providing data and
addresses to the BIU, and for manipulating the general
registers and the flag register. A 16-bit arithmetic/logic
unit (ALU) in the EU maintains the CPU status and con-
trol flags, and manipulates the general registers and in-
struction operands. All registers and data paths in the EU
are 16 bits wide for fast internal transfers.
The EU has no connection to the system bus, the "outside
world." It obtains instructions from a queue maintained
by the BIU. Likewise, when an instruction requires ac-
cess to memory or to a peripheral device, the EU requests
the BIU to obtain and store the data. All addresses manip-
ulated by the EU are 16 bits wide. The BIU, however,
performs an address relocation that gives the EU access to
the full megabyte of memory space.
When the EU is ready to execute an instruction, it fetches
the instruction object code byte from the BIU's instruction
queue and then executes the instruction. If the queue is
1-3
empty when the EU is ready to fetch an instruction byte,
the EU waits for the instruction byte to be fetched. If a
memory location or I/O port must be accessed during the
execution of an instruction, the EU requests the BIU to
perform the required bus cycle.
BUS INTERFACE UNIT
The 8086 and 8088 BIU's are functionally identical, but
are implemented differently to match the structure and
performance characteristics of their respective buses.
Data is transferred between the CPU and memory or I/O
devices upon demand from the EU. The BIU executes all
external bus cycles. This unit consists of the segment and
communications registers, the instruction pointer and the
instruction object code queue. The BIU combines seg-
ment and offset values in a dedicated adder to derive
20-bit addresses, transfers data to and from the EU on the
AL U data bus and loads or "prefetches" instructions into
the queue. These "prefetched" instructions can then be
fetched by the EU with a minimum of wait.
During periods when the EU is busy executing instruc-
tions, the BIU "looks ahead" and fetches more instruc-
tions from memory. These instructions are stored in an
internal RAM array called the instruction stream queu-:.
The 8088 instruction queue holds up to four bytes of the
instruction stream, while the 8086 queue can store up to
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