Intel iAPX 86/88 User Manual page 11

TABLE OF CONTENTS
1-82 8086 Family Multiprocessor System ................................................. 1-98
1-83 8086 Bus Timing-Minimum Mode System ........................................... 1-100
1-84 8086 Bus Timing-Maximum Mode System Using 8288) ................................. 1-102
1-85 Max Mode 8086 with Master 8259A on the local Bus and Slave 8259A's on the System Bus ..... 1-107
1-86 Normally Ready System Inserting a Wait State ......................................... 1-108
1-87 Normally Not Ready System Avoiding a Wait State ...................................... 1-108
1-88 Ready I nputs to the 8284 and Output to the 8086/88 .................................... 1-108
1-89 8284 With 8086/88 Ready Timing ................................................... 1-110
1-90 Using RDY1/RDY2 to Generate Ready ............................................... 1-110
1-91 Using AEN1'/AEN2' to Generate Ready ............................................. 1-110
1-92 Representative Instruction Execution Sequence ....................................... 1-111
1-93 Instruction loop Sequence ........................................................ 1-111
1-94 HOlD/HlDA Sequence Timing Diagram ............................................. 1-112
1-95 DMA Using the 8237-2 ............................................................ 1-114
1-96 8086/88 Minimum System, 8257 on System Bus 16-Bit Transfers .......................... 1-115
1-97 HOlD/HlDA-to/from-RQ '/GT' Conversion Circuit. ..................................... 1-116
1-98 HOlD/HlDA-to/from-RQ'/GT' Conversion Timing ..................................... 1-116
1-99 Request/Grant Sequence Timing ................................................... 1-117
1-100 Channel Transfer Delay Timing ..................................................... 1-117
1-101 Circuit to Translate HOLD into AEN Disable for Maximum Mode 8086/88 .................... 1-118
1-102 8086/88 Bus Conditioning on Reset Timing Diagram .................................... 1-119
1-103 Reset Disable for Max Mode 8086/8088 Bus Interface ................................... 1-119
1-104 Reset Disable for Max Mode 8086/88 Bus Interface in Multi-CPU System .................... 1-120
1-105 Interrupt Vector Table ............................................................. 1-120
1-106 Interrupt Acknowledge Timing ...................................................... 1-123
1-107 NMI During Single Stepping and Normal Single Step Operation ........................... 1-125
1-108 NMI, INTR, Single Step and Divide Error Simultaneous Interrupts .......................... 1-126
1-109 8284A Clock Generator/Driver Block Diagram ......................................... 1-127
1-110 8086/88 Clock Waveform .......................................................... 1-127
1-111 Recommended Crystal Clock Configuration ........................................... 1-127
1-112 8284A I nterfaced to an 8086/88 ..................................................... 1-127
1-113 External Frequency for Multiple 8284's ............................................... 1-128
1-114 Oscillator to ClK and ClK to PClK Timing Relationships ................................ 1-128
1-115 Synchronizing CSYNC With EFI .................................................... 1-128
1-116 CSYNC Setup and Hold to EFI ..................................................... 1-128
1-117 EFI From 8284A Oscillator ......................................................... 1-129
1-118 Synchronizing Multiple 8284As ..................................................... 1-129
1-119 Buffering the 8284 ClK Output ..................................................... 1-129
1-120 8086 and Coprocessor on the local Bus Share a Common 8284 ........................... 1-129
1-121 8284A Reset Circuit. ............................................................. 1-130
1-122 Constant Current Power Up Reset Circuit. ............................................ 1-130
1-123 8086/88 Reset and System Reset. .................................................. 1-130
1-124 8288 Bus Controller Block Diagram ................................................. 1-131
1-125 Status Line Activation and Termination ............................................... 1-132
1-126 Maximum and Minimum Mode Command Timing .................•..................... 1-132
1-127 8289 Bus Arbiter Block Diagram ......................................... , .......... 1-133
1-128 Parallel Priority Resolving Technique ................................................ 1-135
1-129 Higher Priority Arbiter Obtaining the Bus From a lower Priority Arbiter ...................... 1-135
1-130 Serial Priority Resolvi ng .......................................................... 1-136
1-131 Typical Medium Complexity CPU Circuit .............................................. 1-136
1-132 Min Mode 8086 with Master 8259A on the local Bus and Slave 8259A's on the System Bus ..... 1-137
1-133 Max Mode 8086 with Master 8259A on the local Bus and Slave 8259A's on the System Bus ..... 1-138
1-134 MCE Timing to Gate 8259A CAS Address onto the 8086 local Bus ......................... 1-138
1-135 Interrupt Vector Byte ............................................................. 1-139
1-136 Priority Structure Variations-Fully Nested Mode ....................................... 1-139
1-137 IR Triggering Timing Requirements .................................................. 1-141
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