Intel iAPX 86/88 User Manual page 14

TABLE OF CONTENTS
4-3 Register Operands in MOV Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
4-4 Register Operands in Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
4-5 Register Operands in Logical Instructions ............................... , . . . . . . . . . . . .. .4-6
4-6 Typical 8089 Machine Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
4-7 80891/0
Processor Pinout Diagram ................................................. 4-22
4-8 Command Communication Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-24
4-9 CPU/lOP Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 4-24
4-10 iAPX 86/11,88/11 Configuration with 8089 in Local Mode .......... " .................... 4-25
4-11 Typical 8089 Remote Configuration ................................................ " 4-26
4-12 RESET-CA Initialization Timing ..............................•...................... 4-27
4-13 Channel Attention Decoding Circuit ................................................. 4-28
4-14 Channel Command Word Encoding ................................................. 4-28
4-15 Channel Commands ............................................................. 4-29
4-16 Channel State Save Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .. 4-30
4-17 Source Synchronized Transfer Cycle ..................... : ........................... 4-31
4-18 Destination Synchronized Transfer Cycle ............................................. 4-32
4-19 Read Bus Cycle (8-bit Bus) ........................................................ 4-35
4-20 Write Bus Cycle (16-bit Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-36
4-21 Wait State Timing ................................................................ 4-38
4-22 Program Status Word ....................... . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . .. 4-40
5-1 80130 Simplified Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . .. 5-2
5-2 80130 OSP Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
5-3 OSP Typical Configuration With An 8086 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . .. 5-10
5-4 80130 OSP Timing Diagram ....................................................... 5-14
5-5 High-Speed Address Decoding Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .. 5-15
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