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CELO, CEHO : Chip Enable Low/High (Output)
These are the chip enable signals for the V-RAM, and at low
level the RAM is enabled.
Only CELO is used in the system.
2 SRAMs (TC5565), configuration of which is 8k x 8, are used
as the RAM.
The RAM connected to the data buses CCOO-CC07 are assigned
to the even byte, and the one connected to the data buses
ATOO-AT07 are assigned to the odd byte.
2-byte read
operation of display refresh is executed to the V-RAM.
When the CPU or the OMAC reads the V-RAM, two bytes of the
RAM is enabled, but only one of those two bytes is output to
the I/O bus BOOO-BD07.
This is controlled by UAOO input signal.
When UAOO is at low level, one byte of the CCOO-CC07 is
output to the bus BOOO-B007, and when UAOO is at high level,
one byte of the ATOO-AT07 is output to the I/O bus
BDOO-B007.
When the CPU or the OMAC writes to the V-RAM, two bytes of
the RAM is enabled, but only one of those two RAMs executes
the write operation.
WRCO : write Character Code (Output)
WR~O
: write Attribute Data (Output)
These are the write enable signals to the V-RAM.
When the chip enable signal is low and this signal is also
low, write operation to the RAM is executed.
Write operation to the RAM is executed only when the request
signal from the CPU or the OMAC is generated (when both MSLO
and MEWO are low).
In this case, either WRCO or WRAO
becomes low depending on the status of UAOO.
When UAOO is
low, WRCO becomes also low, and write data appears on the
CCOO-CC07 through the I/O buses BOOO-B007.
When UAOO is high, WRA becomes low, and the write data
appears on the ATOO-AT07 through BOOO-B007.
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