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A. 2 BLOCK DIAGRAM
PSRSTO
EXMSLO
DACKoo
<
AtSt
DACKlO-
PAGWRO
20
NMICSO
PAPERtt.o
TEST]
INTl7t
t
<
t
I
RAM
.
'.'~
p:
CGnUoller
::.ROM
I
--
L
Controller
-
DMA
Page
r;:5
Register
--
•
NMI
--
•
Controller
--
•
--
•
~
,
.l
,
r------------~-~-~----- -~
I
I
Inn71
_Iff
i
Port B
~:
,.------------..: I I
Latch
+
I
I
PortC
I
~
TC20UTt
FLTDSLt
PPICSO
ADt1
DACKlO
-20
~
Buffer
~PortA
~
Buffer
~
KBCL1
KBDTt
---+
I
I
I
{
-
K.B. Data
s-p
I
I
--------------------------------------~
Command
-
-
--
-
- -
S20-oo
I
Controller
~L.
DMAEN
IHEO
ADOt
1
DMAEN
IHEO
AD01
OSC141
TEST1
t
WaitJDMA
Controller
14.JIIIIMHZ
I
•
I
lJ
Bus
Controller
I
L-_
-
~ Oock
4.",'.~
Generator
.
.,-
, ...... 7
MADB1
MEWEO
DMESLO
RASTHO
RASTLO
ROMENG
ROMCSO
NMI1
TMGAT1
SPKDRO
KBCLK1
KBDTA1
IRQ11
INTAO
MERDO
MEWRO
IORDO
CALEt
HLDA1
AOI1
WDLAT
WDLENO
IWDlR1
IDLENG
IWHENG
RGTO
(PAOlO
NOY1
DRDY1
CPO.IC1
DMCLK1
TMO.K1
•
•
TEST2
LOWSPO
FIGURE A-2
Block Diagram
A - 2
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