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A.4
DBSCRIP~IORS
OF BACR
PON~IOR
Following are the summarized description about each
functional block in this gate array.
A.4.1 Clock generator
The clock generator receives 14.3ISISMHZ clock, then
generates the CPU clock, DMA clock and Timer clock.
CPU clock
DMA clock
Timer clock
4.77MHz/9.54MHz*
4.77MHz (Duty 50%)
1.ISMHz (Duty 50%)
*
CPU clock rate is changed by selecting one of the two
modes (Fast/Low).
A.4.2 Command decoder
Commands to the I/O controller or memory are generated by
decoding the CPU status.
TABLE A-2
Command Decoder
Command
52
51
50
0
0
0
INTAO
0
0
1
IORDO
0
1
0
IOWRO
0
1
1
(None)
1
0
0
MERDO
1
0
1
MERDO
1
1
0
MEWRO
1
1
1
(None)
A.4.3 Bus controller
The bus controller controls the data bus by decoding
commands mentioned above.
A-10
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