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- Control Signals -
Meanings of each signal described on the previous page are
as follows"
CPUDE
The direction of ODD data bus towards the CPU
BOHEN " BWDIR
CPLDE
The direction of EVEN data bus towards the CPU
WDLEN+BDLEN"BWDIR
ALE
Address Latch Enable
HLDA
IODEN
- IODIR
Holds Acknowledge signal"
During the DMA cycle,
this signal is active"
I/O data bus enable signal"
When a device on the I/O data bus is accessed,
this signal becomes active"
HLDA" (INTA+IODMS) "HLDA"A9"AS" (OCO-OD) " (OES-OEF)
" (IORD+IOWR)
I/O data bus direction signal"
When this sisgnal is
"1",
writing operation is
enabled, and when
non,
reading is enabled"
INTA+IODMS "MERD+IORD"AS "A9
YIODEN
I/O data input/ output buffer is enabled"
SYDEN
IODIR" IODEN"BWDIR" (BDLEN+BDHEN)
SYD bus input/output buffer is enabled"
BWDIR" (BDLEN+BDHEN)
C - 3
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