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A.4.4 8-16 bit conversion controller
8 bit-16 bit conversion is performed by this circuitry when
an 8-bit bus is accessed.
The bus wait timing is controlled
by this circuitry.
A.4.S Wait controller
The wait controller decodes the CPU wait cycle according to
each command described on the previous page by the Bus Ready
signal.
A.4.6 DMA bus controller
The DMA bus controller issues the DMA request signal and
controls the bus.
It issues a bus disconnection request
signal (RQ/GT) to the CPU as a response to the DMAS request
from the DMAC.
It issues HOLDAl signal to theDMAC when the bus is
disconnected, then the DMA cycle starts.
After the DMA
cycle is completed, it changes the bus connection to the CPU
by sending a signal to the RQ/GT gate of the CPU.
A.4.7 DMA Page register
This register is to save the upper 4 bits of the address
lines (A19-A16) during the DMA cycle.
This is composed of 3 sets of 4-bit registers and they are
assigned to the following I/O addresses.
TABLE A-3
DMA Page Register
I/O Address
Command
Description
081
10WR
DMA channel 2 page register
z
- - - - 4
3
2
1
0
I
IA19 IA18 IA17 IA16
I
082
IOWR
DMA channel 3 page register
083
IOWR
DMA channel 1 page register
A - 11
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